X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower.mdwn;h=da186f35b69cb6ad4c6d427ea795e555f6f0888e;hb=b4415717f8b444e7ffa5d4ffbf84f3c9889a8a26;hp=28fe6291534bd60b5c1e21d5afcba985e7d81110;hpb=4f2c8aad9460b275d15bec9d0a1a42b521e9f4df;p=libreriscv.git diff --git a/openpower.mdwn b/openpower.mdwn index 28fe62915..da186f35b 100644 --- a/openpower.mdwn +++ b/openpower.mdwn @@ -1,10 +1,42 @@ +# OpenPOWER + +In the late 1980s [[!wikipedia IBM]] developed a POWER family of processors. +This evolved to a specification known as the POWER ISA. In 2019 IBM made the POWER ISA [[!wikipedia Open_source]], to be looked after by the existing [[!wikipedia OpenPOWER_Foundation]]. Here is a longer history of [[!wikipedia IBM_POWER_microprocessors]]. These IBM proprietary processors +happen to implement what is now known as the POWER ISA. The names +POWER8, POWER9, POWER10 etc. are product designations equivalent to Intel +i5, i7, i9 etc. and are frequently conflated with versions of the POWER ISA (v2.07, v3.0c, v3.1b). + +Libre-SOC is basing its [[Simple-V Vectorisation|sv]] CPU extensions on POWER ISA, because it wants to be able to specify a machine that can be completely trusted, and because POWER, thanks to IBM's involvement, +is designed for high performance. + +See wikipedia page + + +very useful resource describing all assembly instructions + + # Evaluation EULA released! looks good. + -Links +# Links +* OpenPOWER Membership + +* OpenPower HDL Mailing list * [[openpower/isatables]] +* [[openpower/whitepapers]] +* [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec +* [[openpower/gem5]] +* [[openpower/sv]] +* [[openpower/prefix_codes]] Decode/encode prefix-codes, used by JPEG, DEFLATE, etc. +* [[openpower/opcode_regs_deduped]] +* [[openpower/simd_vsx]] +* [[openpower/ISA_WG]] - OpenPOWER ISA Working Group +* [[openpower/pearpc]] +* [[openpower/pipeline_operands]] - the allocation of operands on each pipeline +* [[3d_gpu/architecture/decoder]] * * * @@ -12,6 +44,11 @@ Links * * +PowerPC Unit Tests + +* +* + Summary * FP32 is converted to FP64. Requires SimpleV to be active. @@ -20,19 +57,20 @@ Summary * FCVT between 16/32/64 needed * c++11 atomics not very efficient * no 16/48/64 opcodes, needs a shuffle of opcodes. TODO investigate Power VLE -* needs escape sequencing (ISAMUX/NS) +* needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]] # What we are *NOT* doing: * A processor that is fundamentally incompatible (noncompliant) with Power. (**escape-sequencing requires and guarantees compatibility**). * Opcode 4 Signal Processing (SPE) -* Opcode 4 Vectors or Opcode 60 VSX +* Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions) * Avoidable legacy opcodes +* SIMD. it's awful. # SimpleV -see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below. +see [[openpower/sv]]. SimpleV: a "hardware for-loop" which involves type-casting (both) the register files to "a sequence of elements". The **one** instruction (an unmodified **scalar** instruction) is interpreted as a *hardware @@ -98,6 +136,28 @@ entire row, 2 bits instead of 3. greatly simplifies decoder. * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64 * OP 000-110 and 000-111 for VBLOCK. 11 bits available. +Note that this requires BE instruction encoding (separate from +data BE/LE encoding). BE encoding always places the major opcode in +the first 2 bytes of the raw (uninterpreted) sequential instruction +byte stream. + +Thus in BE-instruction-mode, the first 2 bytes may be analysed to +detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48, +64-bit SVP-64, variable-length VBLOCK, or plain 32-bit. + +It is not possible to distinguish LE-encoded 32-bit instructions +from LE-encoded 16-bit instructions because in LE-encoded 32-bit +instructions, the opcode falls into: + +* bytes 2 and 3 of any given raw (uninterpreted) sequential instruction + byte stream for a 32-bit instruction +* bytes 0 and 1 for a 16-bit Compressed instruction +* bytes 4 and 5 for a 48-bit SVP P48 +* bytes 6 and 7 for a 64-bit SVP P64 + +Clearly this is an impossible situation, therefore BE is the only +option. Note: *this is completely separate from BE/LE for data* + # Compressed 16 Further "escape-sequencing". @@ -120,12 +180,3 @@ Store activation length in a CSR. Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1". -# RISCV userspace - -Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs. - -the exception entry point: -https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409 - -the rest of the context switch code is in a different file: -https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589