X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower.mdwn;h=e174aaeef2d5d06d51c2a2b578f2877c4215e204;hb=12e9237b896ad233cb18946b34dab17d976f415c;hp=1b85356fcb65eb148939e4b2858fcda839a872f0;hpb=4fa43a5b39e84d9755d974183f25f136a902f63a;p=libreriscv.git diff --git a/openpower.mdwn b/openpower.mdwn index 1b85356fc..e174aaeef 100644 --- a/openpower.mdwn +++ b/openpower.mdwn @@ -4,10 +4,24 @@ EULA released! looks good. Links -* https://forums.raptorcs.com/ -* http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev -* http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo -* http://bugs.libre-riscv.org/show_bug.cgi?id=179 +* OpenPower HDL Mailing list +* [[openpower/isatables]] +* [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec +* [[openpower/gem5]] +* [[openpower/pearpc]] +* [[openpower/pipeline_operands]] - the allocation of operands on each pipeline +* [[3d_gpu/architecture/decoder]] +* +* +* +* +* +* + +PowerPC Unit Tests + +* +* Summary @@ -17,7 +31,40 @@ Summary * FCVT between 16/32/64 needed * c++11 atomics not very efficient * no 16/48/64 opcodes, needs a shuffle of opcodes. TODO investigate Power VLE -* needs escape sequencing (ISAMUX/NS) +* needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]] + +# What we are *NOT* doing: + +* A processor that is fundamentally incompatible (noncompliant) with Power. + (**escape-sequencing requires and guarantees compatibility**). +* Opcode 4 Signal Processing (SPE) +* Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions) +* Avoidable legacy opcodes + +# SimpleV + +see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below. +SimpleV: a "hardware for-loop" which involves type-casting (both) the +register files to "a sequence of elements". The **one** instruction +(an unmodified **scalar** instruction) is interpreted as a *hardware +for-loop* that issues **multiple** internal instructions with +sequentially-incrementing register numbers. + +Thus it is completely unnecessary to add any vector opcodes - at all - +saving hugely on both hardware and compiler development time when +the concept is dropped on top of a pre-existing ISA. + +## Condition Registers + +Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1. When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead. + +## Carry + +SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits. + +# Integer Overflow / Saturate + +Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE). To be done instead as CSRs / vector-flags on *standard* arithmetic operations. # atomics @@ -43,6 +90,21 @@ from OpenPower Foundation. This will allow extending ISA (see ISAMUX/NS) in a clean fashion (including for and by OpenPower Foundation) +## Branches in namespaces + +Branches are fine as it is up to the compiler to decide whether to let the +ISAMUX/NS/escape-sequence countdown run out. + +This is all a software / compiler / ABI issue. + +## Function calls in namespaces + +Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out. + +If certain alternative configs are expected, they are part of the function ABI which must be spec'd. + +All of this is a software issue (compiler / ABI). + # Compressed, 48, 64, VBLOCK TODO investigate Power VLE (Freescale doc Ref 314-68105) @@ -55,6 +117,28 @@ entire row, 2 bits instead of 3. greatly simplifies decoder. * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64 * OP 000-110 and 000-111 for VBLOCK. 11 bits available. +Note that this requires BE instruction encoding (separate from +data BE/LE encoding). BE encoding always places the major opcode in +the first 2 bytes of the raw (uninterpreted) sequential instruction +byte stream. + +Thus in BE-instruction-mode, the first 2 bytes may be analysed to +detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48, +64-bit SVP-64, variable-length VBLOCK, or plain 32-bit. + +It is not possible to distinguish LE-encoded 32-bit instructions +from LE-encoded 16-bit instructions because in LE-encoded 32-bit +instructions, the opcode falls into: + +* bytes 2 and 3 of any given raw (uninterpreted) sequential instruction + byte stream for a 32-bit instruction +* bytes 0 and 1 for a 16-bit Compressed instruction +* bytes 4 and 5 for a 48-bit SVP P48 +* bytes 6 and 7 for a 64-bit SVP P64 + +Clearly this is an impossible situation, therefore BE is the only +option. Note: *this is completely separate from BE/LE for data* + # Compressed 16 Further "escape-sequencing". @@ -77,26 +161,12 @@ Store activation length in a CSR. Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1". -## Branches - -Branches are fine as it is up to the compiler to decide whether to let the countdown run out. - -This is all a software / compiler / ABI issue. - -## Function calls. - -Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out. - -If certain alternative configs are expected, they are part of the function ABI which must be spec'd. - -All of this is a software issue (compiler / ABI). - # RISCV userspace Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs. the exception entry point: -https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409 + the rest of the context switch code is in a different file: -https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589 +