X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower.mdwn;h=e174aaeef2d5d06d51c2a2b578f2877c4215e204;hb=e38bf287d056c3d40902741e1026bb20e6fce460;hp=2e1391538e50ed155bf4d4c7f8ea9761a32c7816;hpb=9a4b33cc373b35d95dd755d594917bdd613a20ad;p=libreriscv.git
diff --git a/openpower.mdwn b/openpower.mdwn
index 2e1391538..e174aaeef 100644
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -9,6 +9,7 @@ Links
* [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
* [[openpower/gem5]]
* [[openpower/pearpc]]
+* [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
* [[3d_gpu/architecture/decoder]]
*
*
@@ -30,7 +31,7 @@ Summary
* FCVT between 16/32/64 needed
* c++11 atomics not very efficient
* no 16/48/64 opcodes, needs a shuffle of opcodes. TODO investigate Power VLE
-* needs escape sequencing (ISAMUX/NS)
+* needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
# What we are *NOT* doing:
@@ -165,7 +166,7 @@ Requirements are to have one instruction in each subpage which resets all the wa
Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
the exception entry point:
-https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
+
the rest of the context switch code is in a different file:
-https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589
+