X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower.mdwn;h=ebe663057b32a1e1863c681480136c5c6686d7c9;hb=307b648562744e363f61f26f5cb65c340889bf2c;hp=6dd224dc4fb8a0b13730dea5e843bfce78d14756;hpb=7888fc31e03af04ed25e41e41e46210894b954f8;p=libreriscv.git

diff --git a/openpower.mdwn b/openpower.mdwn
index 6dd224dc4..ebe663057 100644
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -4,10 +4,22 @@ EULA released! looks good.
 
 Links
 
-* https://forums.raptorcs.com/
-* http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev
-* http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo
-* http://bugs.libre-riscv.org/show_bug.cgi?id=179
+* OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
+* [[openpower/isatables]]
+* [[openpower/gem5]]
+* [[openpower/pearpc]]
+* [[3d_gpu/architecture/decoder]]
+* <https://forums.raptorcs.com/>
+* <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
+* <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
+* <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
+* <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
+
+PowerPC Unit Tests
+
+* <https://github.com/lioncash/DolphinPPCTests>
+* <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
 
 Summary
 
@@ -19,6 +31,14 @@ Summary
 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
 * needs escape sequencing (ISAMUX/NS)
 
+# What we are *NOT* doing:
+
+* A processor that is fundamentally incompatible (noncompliant) with Power.
+ (**escape-sequencing requires and guarantees compatibility**).
+* Opcode 4 Signal Processing (SPE)
+* Opcode 4 Vectors or Opcode 60 VSX
+* Avoidable legacy opcodes
+
 # SimpleV
 
 see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
@@ -32,6 +52,18 @@ Thus it is completely unnecessary to add any vector opcodes - at all -
 saving hugely on both hardware and compiler development time when
 the concept is dropped on top of a pre-existing ISA.
 
+## Condition Registers
+
+Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
+
+## Carry
+
+SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
+
+# Integer Overflow / Saturate
+
+Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
+
 # atomics
 
 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
@@ -56,6 +88,21 @@ from OpenPower Foundation.
 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
 (including for and by OpenPower Foundation)
 
+## Branches in namespaces
+
+Branches are fine as it is up to the compiler to decide whether to let the
+ISAMUX/NS/escape-sequence countdown run out.
+
+This is all a software / compiler / ABI issue.
+
+## Function calls in namespaces
+
+Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
+
+If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
+
+All of this is a software issue (compiler / ABI).
+
 # Compressed, 48, 64, VBLOCK
 
 TODO investigate Power VLE (Freescale doc Ref 314-68105)
@@ -90,21 +137,6 @@ Store activation length in a CSR.
 
 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 
-# Branches
-
-Branches are fine as it is up to the compiler to decide whether to let the
-ISAMUX/NS/escape-sequence countdown run out.
-
-This is all a software / compiler / ABI issue.
-
-# Function calls.
-
-Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
-
-If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
-
-All of this is a software issue (compiler / ABI).
-
 # RISCV userspace
 
 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.