X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=passes%2Fcmds%2Fadd.cc;h=a2f4a91000f8e6565c4bcf7b75a6e800a190dfff;hb=c7d71f436d822bbbe3cda118591ed2b33eae3a7f;hp=91f8c2addee6dea783837c9cfac1d7846e8eb1a6;hpb=956ecd48f71417b514c194a833a49238049e00b0;p=yosys.git

diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index 91f8c2add..a2f4a9100 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -116,7 +116,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
 
 struct AddPass : public Pass {
 	AddPass() : Pass("add", "add objects to the design") { }
-	void help() YS_OVERRIDE
+	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -150,7 +150,7 @@ struct AddPass : public Pass {
 		log("Add module[s] with the specified name[s].\n");
 		log("\n");
 	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		std::string command;
 		std::string arg_name;