X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=passes%2Fcmds%2Fscatter.cc;h=a70dd308602877a4dc40e1ddacc35b69724c9b71;hb=b0bee396a8edec360616b68e97a3bd373b700b26;hp=1a780466accd9cd09e12c24ddd11e60d183e9ad5;hpb=b7dda723022ad00c6c0089be888eab319953faa8;p=yosys.git

diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index 1a780466a..a70dd3086 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -22,9 +22,12 @@
 #include "kernel/rtlil.h"
 #include "kernel/log.h"
 
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
 struct ScatterPass : public Pass {
 	ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
-	virtual void help()
+	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -38,35 +41,27 @@ struct ScatterPass : public Pass {
 		log("Use the opt_clean command to get rid of the additional nets.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		CellTypes ct(design);
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto module : design->selected_modules())
 		{
-			if (!design->selected(mod_it.second))
-				continue;
-
-			for (auto &c : mod_it.second->cells)
-			for (auto &p : c.second->connections())
-			{
-				RTLIL::Wire *wire = new RTLIL::Wire;
-				wire->name = NEW_ID;
-				wire->width = p.second.size();
-				mod_it.second->add(wire);
-
-				if (ct.cell_output(c.second->type, p.first)) {
-					RTLIL::SigSig sigsig(p.second, wire);
-					mod_it.second->connect(sigsig);
-				} else {
-					RTLIL::SigSig sigsig(wire, p.second);
-					mod_it.second->connect(sigsig);
+			for (auto cell : module->cells()) {
+				dict<RTLIL::IdString, RTLIL::SigSig> new_connections;
+				for (auto conn : cell->connections())
+					new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second))));
+				for (auto &it : new_connections) {
+					if (ct.cell_output(cell->type, it.first))
+						module->connect(RTLIL::SigSig(it.second.first, it.second.second));
+					else
+						module->connect(RTLIL::SigSig(it.second.second, it.second.first));
+					cell->setPort(it.first, it.second.second);
 				}
-
-				p.second = wire;
 			}
 		}
 	}
 } ScatterPass;
- 
+
+PRIVATE_NAMESPACE_END