X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=passes%2Ffsm%2Ffsm_export.cc;h=8eb1872f0d0eb1a542c03b41919fc2f0cd091b6a;hb=f828cb5132b5d1a2c2d4d26ffaac6d492c7cc69e;hp=2093857b03a756fee0eaf2fb6996ac776ab26d64;hpb=ab747063388e47eab597dad45d91acec88a4ec74;p=yosys.git diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index 2093857b0..8eb1872f0 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -3,11 +3,11 @@ * * Copyright (C) 2012 Clifford Wolf * Copyright (C) 2012 Martin Schmölzer - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -28,14 +28,14 @@ #include #include +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + /** * Convert a signal into a KISS-compatible textual representation. */ std::string kiss_convert_signal(const RTLIL::SigSpec &sig) { - if (!sig.is_fully_const()) { - throw 0; - } - + log_assert(sig.is_fully_const()); return sig.as_const().as_string(); } @@ -49,8 +49,8 @@ std::string kiss_convert_signal(const RTLIL::SigSpec &sig) { * @param module pointer to module which contains the FSM cell. * @param cell pointer to the FSM cell which should be exported. */ -void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::string filename) { - std::map::iterator attr_it; +void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::string filename, bool origenc) { + dict::iterator attr_it; FsmData fsm_data; FsmData::transition_t tr; std::ofstream kiss_file; @@ -59,13 +59,12 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st attr_it = cell->attributes.find("\\fsm_export"); if (!filename.empty()) { - kiss_name.assign(filename); - } else if (attr_it != cell->attributes.end() && attr_it->second.str != "") { - kiss_name.assign(attr_it->second.str); + kiss_name.assign(filename); + } else if (attr_it != cell->attributes.end() && attr_it->second.decode_string() != "") { + kiss_name.assign(attr_it->second.decode_string()); } else { - kiss_name.assign(module->name); - kiss_name.append('-' + cell->name + ".kiss2"); + kiss_name.assign(log_id(module) + std::string("-") + log_id(cell) + ".kiss2"); } log("\n"); @@ -86,15 +85,24 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st kiss_file << ".o " << std::dec << fsm_data.num_outputs << std::endl; kiss_file << ".p " << std::dec << fsm_data.transition_table.size() << std::endl; kiss_file << ".s " << std::dec << fsm_data.state_table.size() << std::endl; - kiss_file << ".r s" << std::dec << fsm_data.reset_state << std::endl; + if (origenc) { + kiss_file << ".r " << kiss_convert_signal(fsm_data.state_table[fsm_data.reset_state]) << std::endl; + } else { + kiss_file << ".r s" << std::dec << fsm_data.reset_state << std::endl; + } for (i = 0; i < fsm_data.transition_table.size(); i++) { tr = fsm_data.transition_table[i]; try { kiss_file << kiss_convert_signal(tr.ctrl_in) << ' '; - kiss_file << 's' << tr.state_in << ' '; - kiss_file << 's' << tr.state_out << ' '; + if (origenc) { + kiss_file << kiss_convert_signal(fsm_data.state_table[tr.state_in]) << ' '; + kiss_file << kiss_convert_signal(fsm_data.state_table[tr.state_out]) << ' '; + } else { + kiss_file << 's' << tr.state_in << ' '; + kiss_file << 's' << tr.state_out << ' '; + } kiss_file << kiss_convert_signal(tr.ctrl_out) << std::endl; } catch (int) { @@ -112,11 +120,11 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st */ struct FsmExportPass : public Pass { FsmExportPass() : Pass("fsm_export", "exporting FSMs to KISS2 files") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" fsm_export [-noauto] [-o filename] [selection]\n"); + log(" fsm_export [-noauto] [-o filename] [-origenc] [selection]\n"); log("\n"); log("This pass creates a KISS2 file for every selected FSM. For FSMs with the\n"); log("'fsm_export' attribute set, the attribute value is used as filename, otherwise\n"); @@ -131,16 +139,20 @@ struct FsmExportPass : public Pass { log(" -o filename\n"); log(" filename of the first exported FSM\n"); log("\n"); + log(" -origenc\n"); + log(" use binary state encoding as state names instead of s0, s1, ...\n"); + log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { - std::map::iterator attr_it; + dict::iterator attr_it; std::string arg; bool flag_noauto = false; std::string filename; + bool flag_origenc = false; size_t argidx; - log_header("Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).\n"); + log_header(design, "Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).\n"); for (argidx = 1; argidx < args.size(); argidx++) { arg = args[argidx]; @@ -153,19 +165,25 @@ struct FsmExportPass : public Pass { filename = args[argidx]; continue; } + if (arg == "-origenc") { + flag_origenc = true; + continue; + } break; } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { attr_it = cell_it.second->attributes.find("\\fsm_export"); if (!flag_noauto || (attr_it != cell_it.second->attributes.end())) { - write_kiss2(mod_it.second, cell_it.second, filename); + write_kiss2(mod_it.second, cell_it.second, filename, flag_origenc); filename.clear(); } } } } FsmExportPass; + +PRIVATE_NAMESPACE_END