X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=passes%2Fproc%2Fproc_arst.cc;h=0874d0981ae6e0b383afd918052c772be08e007c;hb=edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487;hp=cd84cfd5bad57e75934f97efd4088de197a96966;hpb=48ca1ff9ef5bba939348ceeec75ad310afd9fcf8;p=yosys.git

diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index cd84cfd5b..0874d0981 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -262,7 +262,7 @@ struct ProcArstPass : public Pass {
 								for (auto &chunk : act.first.chunks())
 									if (chunk.wire && chunk.wire->attributes.count("\\init")) {
 										RTLIL::SigSpec value = chunk.wire->attributes.at("\\init");
-										value.extend(chunk.wire->width, false);
+										value.extend_xx(chunk.wire->width, false);
 										arst_sig.append(chunk);
 										arst_val.append(value.extract(chunk.offset, chunk.width));
 									}