X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=passes%2Ftechmap%2Fabc9_ops.cc;h=1de95128f515353da933be0bffbd1766727bdc2c;hb=1c88a6c24084743c95db9fb21c2b429a3736fb77;hp=cc82a72cf45761bd45fc21f2224243f2caa09129;hpb=53a99ade9cbab883de5d1dcc30ad89d75266df7f;p=yosys.git

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index cc82a72cf..1de95128f 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -23,6 +23,9 @@
 #include "kernel/utils.h"
 #include "kernel/celltypes.h"
 
+#define ABC9_FLOPS_BASE_ID 8000
+#define ABC9_DELAY_BASE_ID 9000
+
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
@@ -33,6 +36,62 @@ inline std::string remap_name(RTLIL::IdString abc9_name)
 	return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
 }
 
+void check(RTLIL::Design *design)
+{
+	dict<IdString,IdString> box_lookup;
+	for (auto m : design->modules()) {
+		if (m->name.begins_with("$paramod"))
+			continue;
+
+		auto flop = m->get_bool_attribute(ID(abc9_flop));
+		auto it = m->attributes.find(ID(abc9_box_id));
+		if (!flop) {
+			if (it == m->attributes.end())
+				continue;
+			auto id = it->second.as_int();
+			auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
+			if (!r.second)
+				log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
+						log_id(m), id, log_id(r.first->second));
+		}
+
+		// Make carry in the last PI, and carry out the last PO
+		//   since ABC requires it this way
+		IdString carry_in, carry_out;
+		for (const auto &port_name : m->ports) {
+			auto w = m->wire(port_name);
+			log_assert(w);
+			if (w->get_bool_attribute("\\abc9_carry")) {
+				if (w->port_input) {
+					if (carry_in != IdString())
+						log_error("Module '%s' contains more than one (* abc9_carry *) input port.\n", log_id(m));
+					carry_in = port_name;
+				}
+				if (w->port_output) {
+					if (carry_out != IdString())
+						log_error("Module '%s' contains more than one (* abc9_carry *) output port.\n", log_id(m));
+					carry_out = port_name;
+				}
+			}
+		}
+
+		if (carry_in != IdString() && carry_out == IdString())
+			log_error("Module '%s' contains an (* abc9_carry *) input port but no output port.\n", log_id(m));
+		if (carry_in == IdString() && carry_out != IdString())
+			log_error("Module '%s' contains an (* abc9_carry *) output port but no input port.\n", log_id(m));
+
+		if (flop) {
+			int num_outputs = 0;
+			for (auto port_name : m->ports) {
+				auto wire = m->wire(port_name);
+				if (wire->port_output) num_outputs++;
+			}
+			if (num_outputs != 1)
+				log_error("Module '%s' with (* abc_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
+		}
+	}
+}
+
 void mark_scc(RTLIL::Module *module)
 {
 	// For every unique SCC found, (arbitrarily) find the first
@@ -143,7 +202,7 @@ void prep_dff(RTLIL::Module *module)
 	}
 }
 
-void prep_holes(RTLIL::Module *module, bool dff)
+void prep_xaiger(RTLIL::Module *module, bool dff)
 {
 	auto design = module->design;
 	log_assert(design);
@@ -152,20 +211,41 @@ void prep_holes(RTLIL::Module *module, bool dff)
 
 	dict<SigBit, pool<IdString>> bit_drivers, bit_users;
 	TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
-	bool abc9_box_seen = false;
+	dict<IdString, std::vector<IdString>> box_ports;
 
 	for (auto cell : module->cells()) {
 		if (cell->type == "$__ABC9_FF_")
 			continue;
 
 		auto inst_module = module->design->module(cell->type);
-		bool abc9_box = inst_module && inst_module->attributes.count("\\abc9_box_id");
-		bool abc9_flop = false;
-		if (abc9_box) {
-			abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
-			if (abc9_flop && !dff)
-				continue;
-			abc9_box_seen = abc9_box;
+		bool abc9_flop = inst_module && inst_module->get_bool_attribute("\\abc9_flop");
+		if (abc9_flop && !dff)
+			continue;
+
+		if ((inst_module && inst_module->attributes.count("\\abc9_box_id")) || abc9_flop) {
+			auto r = box_ports.insert(cell->type);
+			if (r.second) {
+				// Make carry in the last PI, and carry out the last PO
+				//   since ABC requires it this way
+				IdString carry_in, carry_out;
+				for (const auto &port_name : inst_module->ports) {
+					auto w = inst_module->wire(port_name);
+					log_assert(w);
+					if (w->get_bool_attribute("\\abc9_carry")) {
+						log_assert(w->port_input != w->port_output);
+						if (w->port_input)
+							carry_in = port_name;
+						else if (w->port_output)
+							carry_out = port_name;
+					}
+					else
+						r.first->second.push_back(port_name);
+				}
+				if (carry_in != IdString()) {
+					r.first->second.push_back(carry_in);
+					r.first->second.push_back(carry_out);
+				}
+			}
 		}
 		else if (!yosys_celltypes.cell_known(cell->type))
 			continue;
@@ -183,7 +263,7 @@ void prep_holes(RTLIL::Module *module, bool dff)
 		toposort.node(cell->name);
 	}
 
-	if (!abc9_box_seen)
+	if (box_ports.empty())
 		return;
 
 	for (auto &it : bit_users)
@@ -211,7 +291,13 @@ void prep_holes(RTLIL::Module *module, bool dff)
 
 	log_assert(no_loops);
 
-	vector<Cell*> box_list;
+	RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
+	log_assert(holes_module);
+	holes_module->set_bool_attribute("\\abc9_holes");
+
+	dict<IdString, Cell*> cell_cache;
+
+	int port_id = 1, box_count = 0;
 	for (auto cell_name : toposort.sorted) {
 		RTLIL::Cell *cell = module->cell(cell_name);
 		log_assert(cell);
@@ -220,105 +306,22 @@ void prep_holes(RTLIL::Module *module, bool dff)
 		if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
 			continue;
 
-		bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
+		cell->attributes["\\abc9_box_seq"] = box_count++;
 
-		// Fully pad all unused input connections of this box cell with S0
-		// Fully pad all undriven output connections of this box cell with anonymous wires
-		for (const auto &port_name : box_module->ports) {
-			RTLIL::Wire* w = box_module->wire(port_name);
-			log_assert(w);
-			auto it = cell->connections_.find(port_name);
-			if (w->port_input) {
-				RTLIL::SigSpec rhs;
-				if (it != cell->connections_.end()) {
-					if (GetSize(it->second) < GetSize(w))
-						it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
-					rhs = it->second;
-				}
-				else {
-					rhs = RTLIL::SigSpec(State::S0, GetSize(w));
-					cell->setPort(port_name, rhs);
-				}
-			}
-			if (w->port_output) {
-				RTLIL::SigSpec rhs;
-				auto it = cell->connections_.find(w->name);
-				if (it != cell->connections_.end()) {
-					if (GetSize(it->second) < GetSize(w))
-						it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
-					rhs = it->second;
-				}
-				else {
-					Wire *wire = module->addWire(NEW_ID, GetSize(w));
-					if (blackbox)
-						wire->set_bool_attribute(ID(abc9_padding));
-					rhs = wire;
-					cell->setPort(port_name, rhs);
-				}
-			}
-		}
-
-		cell->attributes["\\abc9_box_seq"] = box_list.size();
-		box_list.emplace_back(cell);
-	}
-	log_assert(!box_list.empty());
-
-	RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
-	log_assert(holes_module);
-	holes_module->set_bool_attribute("\\abc9_holes");
-
-	dict<IdString, Cell*> cell_cache;
-	dict<IdString, std::vector<IdString>> box_ports;
+		IdString derived_type = box_module->derive(design, cell->parameters);
+		box_module = design->module(derived_type);
 
-	int port_id = 1;
-	for (auto cell : box_list) {
-		RTLIL::Module* orig_box_module = design->module(cell->type);
-		log_assert(orig_box_module);
-		IdString derived_name = orig_box_module->derive(design, cell->parameters);
-		RTLIL::Module* box_module = design->module(derived_name);
-
-		auto r = cell_cache.insert(derived_name);
+		auto r = cell_cache.insert(derived_type);
 		auto &holes_cell = r.first->second;
 		if (r.second) {
 			if (box_module->has_processes())
 				Pass::call_on_module(design, box_module, "proc");
 
-			auto r2 = box_ports.insert(cell->type);
-			if (r2.second) {
-				// Make carry in the last PI, and carry out the last PO
-				//   since ABC requires it this way
-				IdString carry_in, carry_out;
-				for (const auto &port_name : box_module->ports) {
-					auto w = box_module->wire(port_name);
-					log_assert(w);
-					if (w->get_bool_attribute("\\abc9_carry")) {
-						if (w->port_input) {
-							if (carry_in != IdString())
-								log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
-							carry_in = port_name;
-						}
-						if (w->port_output) {
-							if (carry_out != IdString())
-								log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
-							carry_out = port_name;
-						}
-					}
-					else
-						r2.first->second.push_back(port_name);
-				}
-
-				if (carry_in != IdString() && carry_out == IdString())
-					log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
-				if (carry_in == IdString() && carry_out != IdString())
-					log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
-				if (carry_in != IdString()) {
-					r2.first->second.push_back(carry_in);
-					r2.first->second.push_back(carry_out);
-				}
-			}
-
 			if (box_module->get_bool_attribute("\\whitebox")) {
-				holes_cell = holes_module->addCell(cell->name, derived_name);
+				holes_cell = holes_module->addCell(cell->name, derived_type);
+
+				if (box_module->has_processes())
+					Pass::call_on_module(design, box_module, "proc");
 
 				int box_inputs = 0;
 				for (auto port_name : box_ports.at(cell->type)) {
@@ -340,7 +343,7 @@ void prep_holes(RTLIL::Module *module, bool dff)
 						}
 					}
 					else if (w->port_output)
-						conn = holes_module->addWire(stringf("%s.%s", derived_name.c_str(), log_id(port_name)), GetSize(w));
+						conn = holes_module->addWire(stringf("%s.%s", derived_type.c_str(), log_id(port_name)), GetSize(w));
 				}
 
 				// For flops only, create an extra 1-bit input that drives a new wire
@@ -379,6 +382,169 @@ void prep_holes(RTLIL::Module *module, bool dff)
 	}
 }
 
+void prep_delays(RTLIL::Design *design)
+{
+	std::set<int> delays;
+	pool<Module*> flops;
+	std::vector<Cell*> cells;
+	dict<IdString,dict<IdString,std::vector<int>>> requireds_cache;
+	for (auto module : design->selected_modules()) {
+		if (module->processes.size() > 0) {
+			log("Skipping module %s as it contains processes.\n", log_id(module));
+			continue;
+		}
+
+		cells.clear();
+		for (auto cell : module->cells()) {
+			if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY)))
+				continue;
+
+			RTLIL::Module* inst_module = module->design->module(cell->type);
+			if (!inst_module)
+				continue;
+			if (!inst_module->get_blackbox_attribute())
+				continue;
+			if (inst_module->get_bool_attribute(ID(abc9_flop))) {
+				IdString derived_type = inst_module->derive(design, cell->parameters);
+				inst_module = design->module(derived_type);
+				log_assert(inst_module);
+				flops.insert(inst_module);
+				continue; // because all flop required times
+				          //   will be captured in the flop box
+			}
+			if (inst_module->attributes.count(ID(abc9_box_id)))
+				continue;
+			cells.emplace_back(cell);
+		}
+
+		delays.clear();
+		for (auto cell : cells) {
+			RTLIL::Module* inst_module = module->design->module(cell->type);
+			log_assert(inst_module);
+			auto &cell_requireds = requireds_cache[cell->type];
+			for (auto &conn : cell->connections_) {
+				auto port_wire = inst_module->wire(conn.first);
+				if (!port_wire->port_input)
+					continue;
+
+				auto r = cell_requireds.insert(conn.first);
+				auto &requireds = r.first->second;
+				if (r.second) {
+					auto it = port_wire->attributes.find("\\abc9_required");
+					if (it == port_wire->attributes.end())
+						continue;
+					if (it->second.flags == 0) {
+						int delay = it->second.as_int();
+						delays.insert(delay);
+						requireds.emplace_back(delay);
+					}
+					else
+						for (const auto &tok : split_tokens(it->second.decode_string())) {
+							int delay = atoi(tok.c_str());
+							delays.insert(delay);
+							requireds.push_back(delay);
+						}
+				}
+
+				if (requireds.empty())
+					continue;
+				if (GetSize(requireds) > 1 && GetSize(requireds) != GetSize(port_wire))
+					log_error("%s.%s is %d bits wide but abc9_required = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
+							GetSize(port_wire), log_signal(port_wire->attributes.at("\\abc9_required")), GetSize(requireds));
+
+				SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
+				auto it = requireds.begin();
+				for (int i = 0; i < GetSize(conn.second); ++i) {
+#ifndef NDEBUG
+					if (ys_debug(1)) {
+						static std::set<std::pair<IdString,IdString>> seen;
+						if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
+					}
+#endif
+					auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
+					box->setPort(ID(I), conn.second[i]);
+					box->setPort(ID(O), O[i]);
+					box->setParam(ID(DELAY), *it);
+					if (requireds.size() > 1)
+						it++;
+					conn.second[i] = O[i];
+				}
+			}
+		}
+
+		std::stringstream ss;
+		bool first = true;
+		for (auto d : delays) {
+			if (first)
+				first = false;
+			else
+				ss << " ";
+			ss << d;
+		}
+		module->attributes[ID(abc9_delays)] = ss.str();
+	}
+
+	int flops_id = ABC9_FLOPS_BASE_ID;
+	std::stringstream ss;
+	for (auto flop_module : flops) {
+		int num_inputs = 0, num_outputs = 0;
+		for (auto port_name : flop_module->ports) {
+			auto wire = flop_module->wire(port_name);
+			if (wire->port_input) num_inputs++;
+			if (wire->port_output) num_outputs++;
+		}
+		log_assert(num_outputs == 1);
+
+		auto r = flop_module->attributes.insert(ID(abc9_box_id));
+		if (r.second)
+			r.first->second = flops_id++;
+
+		ss << log_id(flop_module) << " " << r.first->second.as_int();
+		ss << " 1 " << num_inputs+1 << " " << num_outputs << std::endl;
+		bool first = true;
+		for (auto port_name : flop_module->ports) {
+			auto wire = flop_module->wire(port_name);
+			if (!wire->port_input)
+				continue;
+			if (first)
+				first = false;
+			else
+				ss << " ";
+			ss << wire->attributes.at("\\abc9_required", 0).as_int();
+		}
+		// Last input is 'abc9_ff.Q'
+		ss << " 0" << std::endl << std::endl;
+	}
+	design->scratchpad_set_string("abc9_ops.box.flops", ss.str());
+}
+
+void write_box(RTLIL::Module *module, const std::string &src, const std::string &dst) {
+	std::ofstream ofs(dst);
+	log_assert(ofs.is_open());
+
+	// Since ABC can only accept one box file, we have to copy
+	//   over the existing box file
+	if (src != "(null)") {
+		std::ifstream ifs(src);
+		ofs << ifs.rdbuf() << std::endl;
+		ifs.close();
+	}
+
+	ofs << module->design->scratchpad_get_string("abc9_ops.box.flops");
+
+	auto it = module->attributes.find(ID(abc9_delays));
+	if (it != module->attributes.end()) {
+		for (const auto &tok : split_tokens(it->second.decode_string())) {
+			int d = atoi(tok.c_str());
+			ofs << "$__ABC9_DELAY@" << d << " " << ABC9_DELAY_BASE_ID + d << " 0 1 1" << std::endl;
+			ofs << d << std::endl;
+		}
+		module->attributes.erase(it);
+	}
+
+	ofs.close();
+}
+
 void reintegrate(RTLIL::Module *module)
 {
 	auto design = module->design;
@@ -393,57 +559,6 @@ void reintegrate(RTLIL::Module *module)
 	for (auto w : mapped_mod->wires())
 		module->addWire(remap_name(w->name), GetSize(w));
 
-	dict<IdString,IdString> box_lookup;
-	dict<IdString,std::vector<IdString>> box_ports;
-
-	for (auto m : design->modules()) {
-		auto it = m->attributes.find(ID(abc9_box_id));
-		if (it == m->attributes.end())
-			continue;
-		if (m->name.begins_with("$paramod"))
-			continue;
-		auto id = it->second.as_int();
-		auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
-		if (!r.second)
-			log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
-					log_id(m), id, log_id(r.first->second));
-		log_assert(r.second);
-
-		auto r2 = box_ports.insert(m->name);
-		if (r2.second) {
-			// Make carry in the last PI, and carry out the last PO
-			//   since ABC requires it this way
-			IdString carry_in, carry_out;
-			for (const auto &port_name : m->ports) {
-				auto w = m->wire(port_name);
-				log_assert(w);
-				if (w->get_bool_attribute("\\abc9_carry")) {
-					if (w->port_input) {
-						if (carry_in != IdString())
-							log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
-						carry_in = port_name;
-					}
-					if (w->port_output) {
-						if (carry_out != IdString())
-							log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(m));
-						carry_out = port_name;
-					}
-				}
-				else
-					r2.first->second.push_back(port_name);
-			}
-
-			if (carry_in != IdString() && carry_out == IdString())
-				log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
-			if (carry_in == IdString() && carry_out != IdString())
-				log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
-			if (carry_in != IdString()) {
-				r2.first->second.push_back(carry_in);
-				r2.first->second.push_back(carry_out);
-			}
-		}
-	}
-
 	std::vector<Cell*> boxes;
 	for (auto cell : module->cells().to_vector()) {
 		if (cell->has_keep_attr())
@@ -459,6 +574,7 @@ void reintegrate(RTLIL::Module *module)
 	dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers;
 	dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
 
+	dict<IdString,std::vector<IdString>> box_ports;
 	std::map<IdString, int> cell_stats;
 	for (auto mapped_cell : mapped_mod->cells())
 	{
@@ -511,16 +627,6 @@ void reintegrate(RTLIL::Module *module)
 		}
 
 		if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) {
-			// Convert buffer into direct connection
-			if (mapped_cell->type == ID($lut) &&
-					GetSize(mapped_cell->getPort(ID::A)) == 1 &&
-					mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
-				SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
-				SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
-				module->connect(my_y, my_a);
-				log_abort();
-				continue;
-			}
 			RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
 			cell->parameters = mapped_cell->parameters;
 			cell->attributes = mapped_cell->attributes;
@@ -552,13 +658,27 @@ void reintegrate(RTLIL::Module *module)
 		}
 		else {
 			RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
-			log_assert(existing_cell);
-			log_assert(mapped_cell->type.begins_with("$__boxid"));
-
-			auto type = box_lookup.at(mapped_cell->type, IdString());
-			if (type == IdString())
-				log_error("No module with abc9_box_id = %s found.\n", mapped_cell->type.c_str() + strlen("$__boxid"));
-			mapped_cell->type = type;
+			if (!existing_cell)
+				log_error("Cannot find existing box cell with name '%s' in original design.\n", log_id(mapped_cell));
+#ifndef NDEBUG
+			RTLIL::Module* box_module = design->module(existing_cell->type);
+			IdString derived_type = box_module->derive(design, existing_cell->parameters);
+			RTLIL::Module* derived_module = design->module(derived_type);
+			log_assert(derived_module);
+			log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
+#endif
+			mapped_cell->type = existing_cell->type;
+
+			if (mapped_cell->type == ID($__ABC9_DELAY)) {
+				SigBit I = mapped_cell->getPort(ID(i));
+				SigBit O = mapped_cell->getPort(ID(o));
+				if (I.wire)
+					I.wire = module->wires_.at(remap_name(I.wire->name));
+				log_assert(O.wire);
+				O.wire = module->wires_.at(remap_name(O.wire->name));
+				module->connect(O, I);
+				continue;
+			}
 
 			RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
 			cell->parameters = existing_cell->parameters;
@@ -574,7 +694,6 @@ void reintegrate(RTLIL::Module *module)
 			SigSpec outputs = std::move(it->second);
 			mapped_cell->connections_.erase(it);
 
-			RTLIL::Module* box_module = design->module(mapped_cell->type);
 			auto abc9_flop = box_module->attributes.count("\\abc9_flop");
 			if (!abc9_flop) {
 				for (const auto &i : inputs)
@@ -585,6 +704,31 @@ void reintegrate(RTLIL::Module *module)
 						bit_drivers[i].insert(mapped_cell->name);
 			}
 
+			auto r2 = box_ports.insert(cell->type);
+			if (r2.second) {
+				// Make carry in the last PI, and carry out the last PO
+				//   since ABC requires it this way
+				IdString carry_in, carry_out;
+				for (const auto &port_name : box_module->ports) {
+					auto w = box_module->wire(port_name);
+					log_assert(w);
+					if (w->get_bool_attribute("\\abc9_carry")) {
+						log_assert(w->port_input != w->port_output);
+						if (w->port_input)
+							carry_in = port_name;
+						else if (w->port_output)
+							carry_out = port_name;
+					}
+					else
+						r2.first->second.push_back(port_name);
+				}
+
+				if (carry_in != IdString()) {
+					r2.first->second.push_back(carry_in);
+					r2.first->second.push_back(carry_out);
+				}
+			}
+
 			int input_count = 0, output_count = 0;
 			for (const auto &port_name : box_ports.at(cell->type)) {
 				RTLIL::Wire *w = box_module->wire(port_name);
@@ -609,15 +753,6 @@ void reintegrate(RTLIL::Module *module)
 						c.wire = module->wires_.at(remap_name(c.wire->name));
 					newsig.append(c);
 				}
-
-				auto it = existing_cell->connections_.find(port_name);
-				if (it == existing_cell->connections_.end())
-					continue;
-				if (GetSize(newsig) > GetSize(it->second))
-					newsig = newsig.extract(0, GetSize(it->second));
-				else
-					log_assert(GetSize(newsig) == GetSize(it->second));
-
 				cell->setPort(port_name, newsig);
 
 				if (w->port_input && !abc9_flop)
@@ -770,20 +905,68 @@ struct Abc9OpsPass : public Pass {
 		log("\n");
 		log("    abc9_ops [options] [selection]\n");
 		log("\n");
+		log("This pass contains a set of supporting operations for use during ABC technology\n");
+		log("mapping, and is expected to be called in conjunction with other operations from\n");
+		log("the `abc9' script pass. Only fully-selected modules are supported.\n");
+		log("\n");
+		log("    -check\n");
+		log("        check that the design is valid, e.g. (* abc9_box_id *) values are unique,\n");
+		log("        (* abc9_carry *) is only given for one input/output port, etc.\n");
+		log("\n");
+		log("    -prep_delays\n");
+		log("        insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
+		log("        certain delays, e.g. (* abc9_required *) values.\n");
+		log("\n");
+		log("    -mark_scc\n");
+		log("        for an arbitrarily chosen cell in each unique SCC of each selected module\n");
+		log("        (tagged with an (* abc9_scc_id = <int> *) attribute), temporarily mark all\n");
+		log("        wires driven by this cell's outputs with a (* keep *) attribute in order\n");
+		log("        to break the SCC. this temporary attribute will be removed on -reintegrate.\n");
+		log("\n");
+		log("    -prep_xaiger\n");
+		log("        prepare the design for XAIGER output. this includes computing the\n");
+		log("        topological ordering of ABC9 boxes, as well as preparing the\n");
+		log("        '<module-name>$holes' module that contains the logic behaviour of ABC9\n");
+		log("        whiteboxes.\n");
+		log("\n");
+		log("    -dff\n");
+		log("        consider flop cells (those instantiating modules marked with (* abc9_flop *)\n");
+		log("        during -prep_xaiger.\n");
+		log("\n");
+		log("    -prep_dff\n");
+		log("        compute the clock domain and initial value of each flop in the design.\n");
+		log("        process the '$holes' module to support clock-enable functionality.\n");
+		log("\n");
+		log("    -write_box (<src>|(null)) <dst>\n");
+		log("        copy the existing box file from <src> (skip if '(null)') and append any\n");
+		log("        new box definitions.\n");
+		log("\n");
+		log("    -reintegrate\n");
+		log("        for each selected module, re-intergrate the module '<module-name>$abc9'\n");
+		log("        by first recovering ABC9 boxes, and then stitching in the remaining primary\n");
+		log("        inputs and outputs.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
 
+		bool check_mode = false;
+		bool prep_delays_mode = false;
 		bool mark_scc_mode = false;
 		bool prep_dff_mode = false;
-		bool prep_holes_mode = false;
+		bool prep_xaiger_mode = false;
 		bool reintegrate_mode = false;
 		bool dff_mode = false;
+		std::string write_box_src, write_box_dst;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			std::string arg = args[argidx];
+			if (arg == "-check") {
+				check_mode = true;
+				continue;
+			}
 			if (arg == "-mark_scc") {
 				mark_scc_mode = true;
 				continue;
@@ -792,8 +975,19 @@ struct Abc9OpsPass : public Pass {
 				prep_dff_mode = true;
 				continue;
 			}
-			if (arg == "-prep_holes") {
-				prep_holes_mode = true;
+			if (arg == "-prep_xaiger") {
+				prep_xaiger_mode = true;
+				continue;
+			}
+			if (arg == "-prep_delays") {
+				prep_delays_mode = true;
+				continue;
+			}
+			if (arg == "-write_box" && argidx+2 < args.size()) {
+				write_box_src = args[++argidx];
+				write_box_dst = args[++argidx];
+				rewrite_filename(write_box_src);
+				rewrite_filename(write_box_dst);
 				continue;
 			}
 			if (arg == "-reintegrate") {
@@ -808,11 +1002,16 @@ struct Abc9OpsPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		if (!(mark_scc_mode || prep_dff_mode || reintegrate_mode))
-			log_cmd_error("At least one of -mark_scc, -prep_{dff,holes}, -reintegrate must be specified.\n");
+		if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || !write_box_src.empty() || reintegrate_mode))
+			log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff}, -write_box, -reintegrate must be specified.\n");
+
+		if (dff_mode && !prep_xaiger_mode)
+			log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n");
 
-		if (dff_mode && !prep_holes_mode)
-			log_cmd_error("'-dff' option is only relevant for -prep_holes.\n");
+		if (check_mode)
+			check(design);
+		if (prep_delays_mode)
+			prep_delays(design);
 
 		for (auto mod : design->selected_modules()) {
 			if (mod->get_bool_attribute("\\abc9_holes"))
@@ -826,12 +1025,14 @@ struct Abc9OpsPass : public Pass {
 			if (!design->selected_whole_module(mod))
 				log_error("Can't handle partially selected module %s!\n", log_id(mod));
 
+			if (!write_box_src.empty())
+				write_box(mod, write_box_src, write_box_dst);
 			if (mark_scc_mode)
 				mark_scc(mod);
 			if (prep_dff_mode)
 				prep_dff(mod);
-			if (prep_holes_mode)
-				prep_holes(mod, dff_mode);
+			if (prep_xaiger_mode)
+				prep_xaiger(mod, dff_mode);
 			if (reintegrate_mode)
 				reintegrate(mod);
 		}