X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=pinmux%2Fpinmux_chennai_2018.tex;h=9ca9d640097afe76668327b8faddc0ef1f282e20;hb=5db1e01205aa69eb06cb7f219b9a9884360d4013;hp=b3578ee3b5f9c826e9cfb9b80dc42e7ecb4c85cb;hpb=61bdec20e3261a13c9eb918c7b73a53ccf92ec2e;p=libreriscv.git

diff --git a/pinmux/pinmux_chennai_2018.tex b/pinmux/pinmux_chennai_2018.tex
index b3578ee3b..9ca9d6400 100644
--- a/pinmux/pinmux_chennai_2018.tex
+++ b/pinmux/pinmux_chennai_2018.tex
@@ -66,7 +66,7 @@
          Summary: it's all about making more money!\vspace{4pt}
    \item How? By multiplexing many more functions (100 to 1,200) than there
          are actual available pins (48 to 500), the required chip package
-	     is far less costly and the chip more desirable\vspace{4pt}
+	     is cheaper, smaller, and more versatile\vspace{4pt}
    \item What? A many-to-many dynamically-configureable router of
          I/O functions to I/O pins
   \end{itemize}
@@ -141,7 +141,7 @@
 \frame{\frametitle{Associated Extras}
 
  \begin{itemize}
-   \item Design Specification (what markets to target)
+   \item Design Specification ({\bf what} markets to target)
    \item Scenario analysis ({\bf whether} the chip will fit "markets")
    \item Documentation: Summary sheet, Technical Reference Manual.
    \item Test suites
@@ -190,21 +190,23 @@
 \frame{\frametitle{Reduce workload, reduce duplication, reduce risk and cost}
 
  \begin{itemize}
-   \item Auto-generate everything: documentation, code, libraries etc.
-	     \vspace{10pt}
+   \item Auto-generate everything: documentation, code, libraries etc.\\
+	     (including device-tree files, FreeBSD / Linux / RTOS kernel
+	     drivers, Arduino, libopencm3 and other EC firmware libraries)
+	     \vspace{4pt}
    \item Standardise: similar to PLIC, propose GPIO and Pinmux\\
 	     saves engineering effort, design effort and much more
-	     \vspace{10pt}
+	     \vspace{4pt}
    \item Standardise format of configuration registers:
 	     saves code duplication effort (multiple software environments)
-		 \vspace{10pt}
+		 \vspace{4pt}
    \item Add support for multiple code formats: Chisel3 (SiFive IOF),
 	     BSV (Bluespec), Verilog, VHDL, MyHDL.
-		 \vspace{10pt}
+		 \vspace{4pt}
    \item Multiple auto-generated code-formats permits cross-validation:\\
 	     auto-generated test suite in one HDL can validate a muxer
 	     generated for a different target HDL.
-   		 \vspace{10pt}
+   		 \vspace{4pt}
   \end{itemize}
 }
 
@@ -236,14 +238,14 @@
 \frame{\frametitle{Muxer cases to handle (One/Many to One/Many) etc.}
 
  \begin{itemize}
-   \item One FN outputs to Many Pins: no problem\\
+   \item One FN output to Many Pins: no problem\\
 	     (weird configuration by end-user, but no damage to ASIC)
    \item One Pin to Many FN inputs: no problem\\
          (weird configuration by end-user, but no damage to ASIC)
-   \item Many Pins to One FN input: {\bf Priority Mux needed}\\
-	     No priority mux: Pin1 = HI, Pin0 = LO, ASIC is damaged
    \item Many FN outputs simultaneously to one Pin: {\bf does not occur}\\
 	     (not desirable and not possible, as part of the pinmux design)
+   \item Many Pins to One FN input: {\bf Priority Mux needed}\\
+	     No priority mux: Pin1=HI, Pin0=LO and ASIC is destroyed
    \item Some FNs (I2C\_SDA, SD\_D0..3) are I/O Buses\\
 	     Bi-directional control of the Pin must be handed to the
 	     FN
@@ -258,7 +260,7 @@
 
  In/out: {\bf Note: these all require multiplexing }
  \begin{itemize}
-   \item Output-Enable (aka Input disable): switches pad to In or Out
+   \item Output-Enable (aka Input disable): switches pad to Out or In
    \item Output (actually an input wire controlling pin's level, HI/LO)
    \item Input (actually an output wire set based on pin's driven level)
  \end{itemize}
@@ -286,7 +288,7 @@
 
  \begin{itemize}
    \item Standard Mux design {\bf cannot deal with many-to-one inputs}\\
-	     (SiFive IOF source code from Freedom U310 cannot, either)
+	     (SiFive IOF source code from Freedom E310 cannot, either)
 	     \vspace{4pt}
    \item I/O pad configuration conflated with In-Muxer conflated with
 		 Out-Muxer conflated with GPIO conflated with EINT.
@@ -316,16 +318,22 @@
 
 \frame{\frametitle{GPIO (only): Simplified I/O pad Diagram (FN only)}
  \begin{center}
-  \includegraphics[height=2.5in]{reg_gpio_pinblock.jpg}\\
-  {\bf 3 wires: IN, OUT, OUTEN (also = !INEN) }
+  \includegraphics[height=1.3in]{reg_gpio_pinblock.jpg}
  \end{center}
+ \begin{itemize}
+   \item GPIO In/Out/Direction is just another FN (effectively)
+   \item 3 wires: IN, OUT, OUTEN (=INEN\#)
+   \item FN however may be output-only (UART\_TX), input-only (UART\_RX)
+         or bi-directional (I2C\_SDA) and Bus-controlled.
+   \item GPIO is definitely bi-directional and under Register control
+ \end{itemize}
 }
 
 
 \frame{\frametitle{Output Muxer (very simple)}
  \begin{center}
   \includegraphics[height=1.1in]{reg_gpio_out_mux.jpg}\\
-  {\bf Ouput Muxer using 2-bit address selection}\\
+  {\bf Output Muxer using 2-bit address selection}\\
  \end{center}
  \begin{itemize}
    \item Very straightforward (deceptively so, like SRAM cells)