X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=resources.mdwn;h=229a663ebf1f1b2794af9ba0bcf8aca69baad535;hb=6e1a2638baeb75c3b097c1ae17441c976c4322e9;hp=ee4ba3a3c1669648ae340b5f792731a3145fc2d4;hpb=5535e9fa4d66f3eb7e55283a90079fa16cbd29ef;p=libreriscv.git diff --git a/resources.mdwn b/resources.mdwn index ee4ba3a3c..229a663eb 100644 --- a/resources.mdwn +++ b/resources.mdwn @@ -20,10 +20,12 @@ This section is primarily a series of useful links found online * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0) * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b) +* Virginia Tech course ## Overview of the user ISA: -[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425) +* [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425) +* Power ISA listings ## OpenPOWER OpenFSI Spec (2016) @@ -31,12 +33,31 @@ This section is primarily a series of useful links found online * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf) +# Energy-efficient cores + +* https://arxiv.org/abs/2002.10143 + # Communities * * * +* Open tape-out mailing list + +# ppc64 ELF ABI +* EABI 1.9 supplement +* https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.pdf + +# Other GPU Specifications + +* +* https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf +* https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf +* MALI Midgard +* [Nyuzi](https://github.com/jbush001/NyuziProcessor) +* VideoCore IV +* etnaviv # JTAG @@ -51,8 +72,13 @@ This section is primarily a series of useful links found online # D-Cache +- [A Primer on Memory Consistency and Cache Coherence +](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049) + ## D-Cache Possible Optimizations papers and links - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093) +- [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of +Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901) # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s) @@ -93,7 +119,7 @@ course, we will follow it as well for interoperability. Note: Even though this is such an important standard used by everyone, it is unfortunately not freely available and requires a payment to -access. However, each of the Libre RISC-V members already have access +access. However, each of the Libre-SOC members already have access to the document. * [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html) @@ -112,6 +138,7 @@ Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2 * How not to design an ISA Meester Forsyth + # Khronos Standards The Khronos Group creates open standards for authoring and acceleration @@ -189,14 +216,10 @@ although performance is not evaluated. # Conferences -## Free Silicon Conference +see [[conferences]] -The conference brought together experts and enthusiasts who want to build -a complete Free and Open Source CAD ecosystem for designing analog and -digital integrated circuits. The conference covered the full spectrum of -the design process, from system architecture, to layout and verification. -* +# Coriolis2 * LIP6's Coriolis - a set of backend design tools: @@ -204,8 +227,19 @@ the design process, from system architecture, to layout and verification. Note: The rest of LIP6's website is in French, but there is a UK flag in the corner that gives the English version. +# Logical Equivalence and extraction + +* NETGEN +* CVC https://github.com/d-m-bailey/cvc + +# Klayout + * KLayout - Layout viewer and editor: +# image to GDS-II + +* https://nazca-design.org/convert-image-to-gds/ + # The OpenROAD Project OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source @@ -279,6 +313,8 @@ thousands or millions of silicon. * Possible way to speed up our solvers for our formal proofs * Algorithms (papers) submitted for 2018 International SAT Competition +* Minisail - compiler + for SAIL into c Some learning resources I found in the community: @@ -290,10 +326,31 @@ Some learning resources I found in the community: * * +VAMP CPU + +* Formal verification of a fully IEEE compliant floating point unit + +* +* the PVS/hw subfolder is under the 2-clause BSD license: + +* + ## Automation * +# Bus Architectures + +* Avalon +* CXM + +# Vector Processors + +* THOR +* NEC SX-Aurora +* RVV +* MRISC32 + # LLVM ## Adding new instructions: @@ -306,11 +363,9 @@ Some learning resources I found in the community: # Python RTL Tools +* pylog fpga + * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/) -* [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers) - An SOC builder written in Python Migen DSL. Allows you to generate functional - RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support, - and parameterizeable CSRs. * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>) * There is a great guy, Robert Baruch, who has a good [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen. @@ -318,16 +373,18 @@ Some learning resources I found in the community: [the code](https://github.com/RobertBaruch/n6800) and [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw) online. -* [Minerva](https://github.com/lambdaconcept/minerva) - An SOC written in Python nMigen DSL -* Minerva example using nmigen-soc - + There is now a page [[docs/learning_nmigen]]. * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html) * -* # Other +* 10-bit SAR ADC +* Cray-1 Pocket Reference + + + +* Prefix-tree generation scripts * N1 * Libre Cell Library * @@ -335,6 +392,8 @@ Some learning resources I found in the community: * * pipeline skid buffer * GTKwave +* - console-based vcd viewer +* - Waveform Analysis * Synchronous Resets? Asynchronous Resets? I am so confused! How will I ever know which to use? by Clifford E. Cummings @@ -347,7 +406,7 @@ Some learning resources I found in the community: Understanding Latency Hiding on GPUs, by Vasily Volkov * Efabless "Openlane" * example of openlane with nmigen - + * Co-simulation plugin for verilator, transferring to ECP5 * Multi-read/write ported memories @@ -361,7 +420,10 @@ Some learning resources I found in the community: * Circuit of Compunit * Circuitverse 16-bit * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance. - + +* adrian_b architecture comparison +* ericandecscent RISC-V + # Real/Physical Projects * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu) @@ -468,9 +530,14 @@ This list auto-generated from a page tag "standards": * * +# Handy Compiler Algorithms for SimpleV + +* [Graph Coloring Register Allocation for Processors with Multi-Register Operands](https://dl.acm.org/doi/pdf/10.1145/93548.93552) + # TODO investigate ``` + https://www.nextplatform.com/2022/08/22/the-expanding-cxl-memory-hierarchy-is-inevitable-and-good-enough/ https://github.com/idea-fasoc/OpenFASOC https://www.quicklogic.com/2020/06/18/the-tipping-point/ https://www.quicklogic.com/blog/ @@ -492,4 +559,7 @@ This list auto-generated from a page tag "standards": OpenTitan also uses FuseSoC LowRISC is UK based https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/ + https://cirosantilli.com/x86-paging + https://stackoverflow.com/questions/18431261/how-does-x86-paging-work + http://denninginstitute.com/modules/vm/red/i486page.html ```