X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=resources.mdwn;h=26c8b314c81b30f8c2eb496697e678bca8733780;hb=ca3aaff24c11e484cb18cdedfda92325a8e7c815;hp=d1c113ebe98e8ac8854ba94ae958ab46ac936594;hpb=1804334535fcfbe92a0f8abf5fb5399963032cf1;p=libreriscv.git diff --git a/resources.mdwn b/resources.mdwn index d1c113ebe..26c8b314c 100644 --- a/resources.mdwn +++ b/resources.mdwn @@ -21,6 +21,16 @@ This section is primarily a series of useful links found online * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0) * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b) +## Overview of the user ISA: + +[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425) + +## OpenPOWER OpenFSI Spec (2016) + +* [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf) + +* [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf) + # RISC-V Instruction Set Architecture **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space @@ -47,6 +57,14 @@ at the moment. However, there are many wiki pages that make a reference to the V extension so it would be good to include it here as a reference for comparative/informative purposes with regard to Simple-V. +# Radix MMU + - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182) + +# D-Cache + +## D-Cache Possible Optimizations papers and links +- [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093) + # RTL Arithmetic SQRT, FPU etc. @@ -54,6 +72,17 @@ for comparative/informative purposes with regard to Simple-V. * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf) * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf) +## CORDIC and related algorithms + +* research into CORDIC +* +* [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm) +* [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf) + - Does not have an easy way of computing tan(x) +* [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html) +* [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access) +* MyHDL version of CORDIC + ## IEEE Standard for Floating-Point Arithmetic (IEEE 754) Almost all modern computers follow the IEEE Floating-Point Standard. Of @@ -66,6 +95,20 @@ it is unfortunately not freely available and requires a payment to access. However, each of the Libre RISC-V members already have access to the document. +* [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html) + +Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit. + +* [What Every Computer Scientist Should Know About Floating-Point Arithmetic](https://docs.oracle.com/cd/E19957-01/806-3568/ncg_goldberg.html) + +Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma". + +## Past FPU Mistakes to learn from + +* [Intel Underestimates Error Bounds by 1.3 quintillion on +Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/) +* [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy) + # Khronos Standards The Khronos Group creates open standards for authoring and acceleration @@ -94,6 +137,11 @@ switching between different accuracy levels, in userspace applications. * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html) * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html) +* OpenCL released the proposed OpenCL 3.0 spec for comments in april 2020 + +* [Announcement video](https://youtu.be/h0_syTg6TtY) +* [Announcement video slides (PDF)](https://www.khronos.org/assets/uploads/apis/OpenCL-3.0-Launch-Apr20.pdf) + Note: We are implementing hardware accelerated Vulkan and OpenCL while relying on other software projects to translate APIs to Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software. @@ -106,6 +154,11 @@ although performance is not evaluated. +* Pixilica is heading up an initiative to create a RISC-V graphical ISA + +* [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf) + + # Various POWER Communities - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/) The T2080 is a POWER8 chip. @@ -172,11 +225,13 @@ test. It's still in development as far as I can tell. IEEE 754 has no official tests for floating-point but there are well-known third party tools to check such as John Hauser's TestFloat. -There is also his SoftFloat library, which is a software emulation library for IEEE 754. +There is also his SoftFloat library, which is a software emulation +library for IEEE 754. * -Jacob is also working on an IEEE 754 software emulation library written in Rust which also has Python bindings: +Jacob is also working on an IEEE 754 software emulation library written +in Rust which also has Python bindings: * Source: * Crate: @@ -211,16 +266,13 @@ thousands or millions of silicon. Some learning resources I found in the community: -* ZipCPU: - -ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizzes/slides: - - -* Western Digital's SweRV CPU blog (I recommend looking at all their posts): - - - - +* ZipCPU: ZipCPU provides a comprehensive + tutorial for beginners and many exercises/quizzes/slides: + +* Western Digital's SweRV CPU blog (I recommend looking at all their + posts): +* +* ## Automation @@ -236,26 +288,52 @@ ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizze * - # Python RTL Tools + * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/) * [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers) An SOC builder written in Python Migen DSL. Allows you to generate functional RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support, and parameterizeable CSRs. * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>) +* There is a great guy, Robert Baruch, who has a good + [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen. + He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put + [the code](https://github.com/RobertBaruch/n6800) and + [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw) + online. * [Minerva](https://github.com/lambdaconcept/minerva) An SOC written in Python nMigen DSL - * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html) * * +# Other -## Other * +* +* +* pipeline skid buffer +* GTKwave +* + Synchronous Resets? Asynchronous Resets? I am so confused! How will I + ever know which to use? by Clifford E. Cummings +* + Clock Domain Crossing (CDC) Design & Verification Techniques Using + SystemVerilog, by Clifford E. Cummings + In particular, see section 5.8.2: Multi-bit CDC signal passing using + 1-deep / 2-register FIFO synchronizer. +* + Understanding Latency Hiding on GPUs, by Vasily Volkov +* Efabless "Openlane" +* Co-simulation plugin for verilator, transferring to ECP5 + +* Multi-read/write ported memories + + # Real/Physical Projects + * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu) * * @@ -265,24 +343,30 @@ ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizze * * +# ASIC tape-out pricing + +* + # Funding + * * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02) # Good Programming/Design Practices + * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle) * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment) * * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/) - - * * -* Fundamentals of Modern VLSI Devices +* Fundamentals of Modern VLSI Devices + + +# 12 skills summary -# Broken Links -* +* # Analog Simulation @@ -291,7 +375,7 @@ ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizze * * -# Libre-RISC-V Standards +# Libre-SOC Standards This list auto-generated from a page tag "standards": @@ -299,4 +383,28 @@ This list auto-generated from a page tag "standards": # Server setup -[[resources/server-setup/git-mirroring]] +* [[resources/server-setup/web-server]] +* [[resources/server-setup/git-mirroring]] +* [[resources/server-setup/nagios-monitoring]] + +# Testbeds + +* + +# Really Useful Stuff + +* +* + +# Digilent Arty + +* https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/ +* https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/ +* https://store.digilentinc.com/pmod-vga-video-graphics-array/ +* https://store.digilentinc.com/pmod-microsd-microsd-card-slot/ +* https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/ +* https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/ + +# CircuitJS experiments + +* [[resources/high-speed-serdes-in-circuitjs]]