X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=resources.mdwn;h=2721221013e97515078677247386204c2132311b;hb=4dfc32a35c24dcd9e0f05010b4e5c1bd1360bf17;hp=aa08eeed2b43b85e923c51da2445635289be27e3;hpb=29aca3237588221e2608ee85592163a8d953fea2;p=libreriscv.git diff --git a/resources.mdwn b/resources.mdwn index aa08eeed2..272122101 100644 --- a/resources.mdwn +++ b/resources.mdwn @@ -20,10 +20,14 @@ This section is primarily a series of useful links found online * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0) * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b) +* Virginia Tech course +* mini functional simulator https://github.com/god-s-perfect-idiot/POWER-sim +* https://raw.githubusercontent.com/linuxppc/public-docs/main/ISA/PowerPC_Assembly_IBM_Programming_Environment_2.3.pdf ## Overview of the user ISA: -[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425) +* [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425) +* Power ISA listings ## OpenPOWER OpenFSI Spec (2016) @@ -34,6 +38,11 @@ This section is primarily a series of useful links found online # Energy-efficient cores * https://arxiv.org/abs/2002.10143 +* https://arxiv.org/abs/2011.08070 + +# Open Access Publication locations + +* # Communities @@ -42,6 +51,17 @@ This section is primarily a series of useful links found online * * Open tape-out mailing list +# ppc64 ELF ABI + +* EABI 1.9 supplement +* https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.pdf +* v2.1.5 + +# Similar concepts + +* Vector registers may be + made "ultra-wide" (SX Aurora / Cray) + # Other GPU Specifications * @@ -319,6 +339,15 @@ Some learning resources I found in the community: * * +VAMP CPU + +* Formal verification of a fully IEEE compliant floating point unit + +* +* the PVS/hw subfolder is under the 2-clause BSD license: + +* + ## Automation * @@ -328,6 +357,13 @@ Some learning resources I found in the community: * Avalon * CXM +# Vector Processors + +* THOR +* NEC SX-Aurora +* RVV +* MRISC32 + # LLVM ## Adding new instructions: @@ -340,11 +376,9 @@ Some learning resources I found in the community: # Python RTL Tools +* pylog fpga + * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/) -* [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers) - An SOC builder written in Python Migen DSL. Allows you to generate functional - RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support, - and parameterizeable CSRs. * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>) * There is a great guy, Robert Baruch, who has a good [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen. @@ -353,16 +387,17 @@ Some learning resources I found in the community: [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw) online. There is now a page [[docs/learning_nmigen]]. -* [Minerva](https://github.com/lambdaconcept/minerva) - An SOC written in Python nMigen DSL -* Minerva example using nmigen-soc - * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html) * -* # Other +* 10-bit SAR ADC +* Cray-1 Pocket Reference + + + +* Prefix-tree generation scripts * N1 * Libre Cell Library * @@ -370,6 +405,7 @@ Some learning resources I found in the community: * * pipeline skid buffer * GTKwave +* - console-based vcd viewer * - Waveform Analysis * Synchronous Resets? Asynchronous Resets? I am so confused! How will I @@ -397,7 +433,9 @@ Some learning resources I found in the community: * Circuit of Compunit * Circuitverse 16-bit * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance. - + +* adrian_b architecture comparison +* ericandecscent RISC-V # Real/Physical Projects @@ -424,7 +462,7 @@ Some learning resources I found in the community: * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle) * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment) * -* [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/) +* [It's not a zero-sum game](https://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/) * * @@ -505,9 +543,20 @@ This list auto-generated from a page tag "standards": * * +# Handy Compiler Algorithms for SimpleV + +Requires aligned registers: + +* [Graph Coloring Register Allocation for Processors with Multi-Register Operands](https://dl.acm.org/doi/pdf/10.1145/93548.93552) + +More general: + +* [Retargetable Graph-Coloring Register Allocation for Irregular Architectures](https://user.it.uu.se/~svenolof/wpo/AllocSCOPES2003.20030626b.pdf) + # TODO investigate ``` + https://www.nextplatform.com/2022/08/22/the-expanding-cxl-memory-hierarchy-is-inevitable-and-good-enough/ https://github.com/idea-fasoc/OpenFASOC https://www.quicklogic.com/2020/06/18/the-tipping-point/ https://www.quicklogic.com/blog/ @@ -529,4 +578,7 @@ This list auto-generated from a page tag "standards": OpenTitan also uses FuseSoC LowRISC is UK based https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/ + https://cirosantilli.com/x86-paging + https://stackoverflow.com/questions/18431261/how-does-x86-paging-work + http://denninginstitute.com/modules/vm/red/i486page.html ```