X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=resources.mdwn;h=40ef278e0114e0137496851c17a0d67ba80805c9;hb=d746ebf4836f1ed7a56a7e3dfb1cb8e5ee1aa9cc;hp=b23863f4c7658e065fa60dd6302a884923c0ba37;hpb=274951a01882daa91ab1b21c114ba4676905e00c;p=libreriscv.git

diff --git a/resources.mdwn b/resources.mdwn
index b23863f4c..40ef278e0 100644
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -48,7 +48,7 @@ This section is primarily a series of useful links found online
 * https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf 
 * https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf 
 * MALI Midgard
-* Nyuzi
+* [Nyuzi](https://github.com/jbush001/NyuziProcessor)
 * VideoCore IV
 * etnaviv
 
@@ -65,8 +65,13 @@ This section is primarily a series of useful links found online
 
 # D-Cache
 
+- [A Primer on Memory Consistency and Cache Coherence
+](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049)
+
 ## D-Cache Possible Optimizations papers and links
 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
+- [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
+Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901)
 
 # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
 - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
@@ -313,6 +318,11 @@ Some learning resources I found in the community:
 
 * <https://www.ohwr.org/project/wishbone-gen>
 
+# Bus Architectures
+
+* Avalon <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf>
+* CXM <https://www.computeexpresslink.org/download-the-specification>
+
 # LLVM
 
 ## Adding new instructions: