X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=resources.mdwn;h=42851192db79fa82422cf0120c1b9a34547bda2e;hb=7f14f8aaef0ee86c26a4f4b0913e08cada0c41bf;hp=2689a3fd97277855a08024e20641e2a4be7a076b;hpb=81f1c0e4695fcd7de5934454cd4917c671116e4b;p=libreriscv.git

diff --git a/resources.mdwn b/resources.mdwn
index 2689a3fd9..42851192d 100644
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -23,7 +23,8 @@ This section is primarily a series of useful links found online
 
 ## Overview of the user ISA:
 
-[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* Power ISA listings <https://power-isa-beta.mybluemix.net/>
 
 ## OpenPOWER OpenFSI Spec (2016)
 
@@ -31,12 +32,26 @@ This section is primarily a series of useful links found online
 
 * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
 
+# Energy-efficient cores
+
+* https://arxiv.org/abs/2002.10143
+
 # Communities
 
 * <https://www.reddit.com/r/OpenPOWER/>
 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
+* Open tape-out mailing list <https://groups.google.com/a/opentapeout.dev/g/mailinglist>
 
+# Other GPU Specifications
+
+* 
+* https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf 
+* https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf 
+* MALI Midgard
+* [Nyuzi](https://github.com/jbush001/NyuziProcessor)
+* VideoCore IV
+* etnaviv
 
 # JTAG
 
@@ -51,8 +66,13 @@ This section is primarily a series of useful links found online
 
 # D-Cache
 
+- [A Primer on Memory Consistency and Cache Coherence
+](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049)
+
 ## D-Cache Possible Optimizations papers and links
 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
+- [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
+Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901)
 
 # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
 - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
@@ -112,6 +132,7 @@ Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2
 * How not to design an ISA
  <https://player.vimeo.com/video/450406346>
   Meester Forsyth <http://eelpi.gotdns.org/>
+
 # Khronos Standards
 
 The Khronos Group creates open standards for authoring and acceleration
@@ -189,14 +210,10 @@ although performance is not evaluated.
 
 # Conferences
 
-## Free Silicon Conference
+see [[conferences]]
 
-The conference brought together experts and enthusiasts who want to build
-a complete Free and Open Source CAD ecosystem for designing analog and
-digital integrated circuits.  The conference covered the full spectrum of
-the design process, from system architecture, to layout and verification.
 
-* <https://wiki.f-si.org/index.php/FSiC2019#Foundries.2C_PDKs_and_cell_libraries>
+# Coriolis2
 
 * LIP6's Coriolis - a set of backend design tools:
   <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
@@ -204,8 +221,19 @@ the design process, from system architecture, to layout and verification.
 Note: The rest of LIP6's website is in French, but there is a UK flag
 in the corner that gives the English version.
 
+# Logical Equivalence and extraction
+
+* NETGEN
+* CVC https://github.com/d-m-bailey/cvc
+
+# Klayout
+
 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
 
+# image to GDS-II
+
+* https://nazca-design.org/convert-image-to-gds/
+ 
 # The OpenROAD Project
 
 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
@@ -279,6 +307,8 @@ thousands or millions of silicon.
 * Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
 
 * Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
+* Minisail <https://www.isa-afp.org/entries/MiniSail.html> - compiler
+  for SAIL into c
 
 Some learning resources I found in the community:
 
@@ -294,6 +324,18 @@ Some learning resources I found in the community:
 
 * <https://www.ohwr.org/project/wishbone-gen>
 
+# Bus Architectures
+
+* Avalon <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf>
+* CXM <https://www.computeexpresslink.org/download-the-specification>
+
+# Vector Processors
+
+* THOR <https://github.com/robfinch/Thor/blob/main/Thor2021/doc/Thor2021.pdf>
+* NEC SX-Aurora
+* RVV
+* MRISC32 <https://github.com/mrisc32/mrisc32>
+
 # LLVM
 
 ## Adding new instructions:
@@ -318,13 +360,13 @@ Some learning resources I found in the community:
   [the code](https://github.com/RobertBaruch/n6800) and
   [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
   online.
+  There is now a page [[docs/learning_nmigen]].
 * [Minerva](https://github.com/lambdaconcept/minerva)
   An SOC written in Python nMigen DSL
 * Minerva example using nmigen-soc
   <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
-* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
 
 # Other
 
@@ -335,6 +377,7 @@ Some learning resources I found in the community:
 * <https://www.lowrisc.org/open-silicon/>
 * <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
 * <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
+* <https://github.com/ics-jku/wal> - Waveform Analysis
 * <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
   Synchronous Resets? Asynchronous Resets? I am so confused! How will I
   ever know which to use? by Clifford E. Cummings
@@ -347,7 +390,7 @@ Some learning resources I found in the community:
   Understanding Latency Hiding on GPUs, by Vasily Volkov
 * Efabless "Openlane" <https://github.com/efabless/openlane>
 * example of openlane with nmigen
-  <https://gist.github.com/lethalbit/e65e296bc6a3810280d1b256c9df591b>
+  <https://github.com/lethalbit/nmigen/tree/openlane>
 * Co-simulation plugin for verilator, transferring to ECP5
   <https://github.com/vmware/cascade>
 * Multi-read/write ported memories
@@ -362,6 +405,7 @@ Some learning resources I found in the community:
 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
 <https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf> 
+
 # Real/Physical Projects
 
 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
@@ -492,4 +536,6 @@ This list auto-generated from a page tag "standards":
      OpenTitan also uses FuseSoC
      LowRISC is UK based
      https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
+    https://cirosantilli.com/x86-paging
+    http://denninginstitute.com/modules/vm/red/i486page.html
 ```