X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=resources.mdwn;h=723dab28c8b4fe5f89716114488e457cbf9f5165;hb=3a1627846ef5641638088ec7f31903586f0c433b;hp=85ef2d2e5ed44998b240f2316e87103c0974a7f6;hpb=e97bbb11c726e2d9910b4555a5afe5ffee39baf5;p=libreriscv.git diff --git a/resources.mdwn b/resources.mdwn index 85ef2d2e5..723dab28c 100644 --- a/resources.mdwn +++ b/resources.mdwn @@ -31,6 +31,13 @@ This section is primarily a series of useful links found online * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf) +# Communities + +* +* +* + + # JTAG * [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf) @@ -39,32 +46,6 @@ This section is primarily a series of useful links found online "The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications." -# RISC-V Instruction Set Architecture - -**PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space -RISCV - -The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name -of the project implies, we will be following the RISC-V ISA I due to it -being open-source and also because of the huge software and hardware -ecosystem building around it. There are other open-source ISAs but none -of them have the same momentum and energy behind it as RISC-V. - -To fully take advantage of the RISC-V ecosystem, it is important to be -compliant with the RISC-V standards. Doing so will allow us to to reuse -most software as-is and avoid major forks. - -* [Official compiled PDFs of RISC-V ISA Manual] - (https://github.com/riscv/riscv-isa-manual/releases/latest) -* [Working draft of the proposed RISC-V Bitmanipulation extension](https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf) -* [RISC-V "V" Vector Extension](https://riscv.github.io/documents/riscv-v-spec/) -* [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md) - -Note: As far as I know, we aren't using the RISC-V V Extension directly -at the moment. However, there are many wiki pages that make a reference -to the V extension so it would be good to include it here as a reference -for comparative/informative purposes with regard to Simple-V. - # Radix MMU - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182) @@ -80,9 +61,16 @@ for comparative/informative purposes with regard to Simple-V. # RTL Arithmetic SQRT, FPU etc. +## Wallace vs Dadda Multipliers + +* [Paper comparing efficiency of Wallace and Dadda Multipliers in RTL implementations (clicking will download the pdf from archive.org)](https://web.archive.org/web/20180717013227/http://ieeemilestones.ethw.org/images/d/db/A_comparison_of_Dadda_and_Wallace_multiplier_delays.pdf) + ## Sqrt * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf) * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf) +* [Fast Calculation of Cube and Inverse Cube Roots Using a Magic Constant and Its Implementation on Microcontrollers (clicking will download the pdf)](https://res.mdpi.com/d_attachment/energies/energies-14-01058/article_deploy/energies-14-01058-v2.pdf) +* [Modified Fast Inverse Square Root and Square Root Approximation Algorithms: The Method of Switching Magic Constants (clicking will download the pdf)](https://res.mdpi.com/d_attachment/computation/computation-09-00021/article_deploy/computation-09-00021-v3.pdf) + ## CORDIC and related algorithms @@ -94,6 +82,7 @@ for comparative/informative purposes with regard to Simple-V. * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html) * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access) * MyHDL version of CORDIC +* ## IEEE Standard for Floating-Point Arithmetic (IEEE 754) @@ -104,7 +93,7 @@ course, we will follow it as well for interoperability. Note: Even though this is such an important standard used by everyone, it is unfortunately not freely available and requires a payment to -access. However, each of the Libre RISC-V members already have access +access. However, each of the Libre-SOC members already have access to the document. * [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html) @@ -120,6 +109,9 @@ Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilem * [Intel Underestimates Error Bounds by 1.3 quintillion on Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/) * [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy) +* How not to design an ISA + + Meester Forsyth # Khronos Standards @@ -158,6 +150,10 @@ Note: We are implementing hardware accelerated Vulkan and OpenCL while relying on other software projects to translate APIs to Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software. +# Open Source (CC BY + MIT) DirectX specs (by Microsoft, but not official specs) + +https://github.com/Microsoft/DirectX-Specs + # Graphics and Compute API Stack I found this informative post that mentions Kazan and a whole bunch of @@ -281,6 +277,10 @@ regards to what we specify. Of course, it is important to do the formal verification as a final step in the development process before we produce thousands or millions of silicon. +* Possible way to speed up our solvers for our formal proofs + +* Algorithms (papers) submitted for 2018 International SAT Competition + Some learning resources I found in the community: * ZipCPU: ZipCPU provides a comprehensive @@ -321,12 +321,16 @@ Some learning resources I found in the community: online. * [Minerva](https://github.com/lambdaconcept/minerva) An SOC written in Python nMigen DSL +* Minerva example using nmigen-soc + * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html) * * # Other +* N1 +* Libre Cell Library * * * @@ -343,6 +347,8 @@ Some learning resources I found in the community: * Understanding Latency Hiding on GPUs, by Vasily Volkov * Efabless "Openlane" +* example of openlane with nmigen + * Co-simulation plugin for verilator, transferring to ECP5 * Multi-read/write ported memories @@ -351,8 +357,12 @@ Some learning resources I found in the community: * OpenPOWER Foundation Membership - - +* Clock switching (and formal verification) + +* Circuit of Compunit +* Circuitverse 16-bit +* Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance. + # Real/Physical Projects * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu) @@ -430,8 +440,57 @@ This list auto-generated from a page tag "standards": * [[resources/high-speed-serdes-in-circuitjs]] +# Logic Simulator 2 +* +[Live web version](https://dkilfoyle.github.io/logic2/) + +> ## Features +> 1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr) +> 2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints +> 3. IDE docking ui courtesy of JupyterLab's Lumino widgets +> 4. Schematic visualisation courtesy of d3-hwschematic +> 5. Testbench simulation with graphical trace output and schematic animation +> 6. Circuit description as gates, boolean logic or verilog behavioural model +> 7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map + +[from the GitHub page. As of 2021/03/29] + # ASIC Timing and Design flow resources * * * +* + +# Geometric Haskell Library + +* +* +* +* + +# TODO investigate + +``` + https://github.com/idea-fasoc/OpenFASOC + https://www.quicklogic.com/2020/06/18/the-tipping-point/ + https://www.quicklogic.com/blog/ + https://www.quicklogic.com/2020/09/15/why-open-source-ecosystems-make-good-business-sense/ + https://www.quicklogic.com/qorc/ + https://en.wikipedia.org/wiki/RAD750 + The RAD750 system has a price that is comparable to the RAD6000, the latter of which as of 2002 was listed at US$200,000 (equivalent to $284,292 in 2019). + https://theamphour.com/525-open-fpga-toolchains-and-machine-learning-with-brian-faith-of-quicklogic/ + https://github.blog/2021-03-22-open-innovation-winning-strategy-digital-sovereignty-human-progress/ + https://github.com/olofk/edalize + https://github.com/hdl/containers + https://twitter.com/OlofKindgren/status/1374848733746192394 + You might also want to check out https://umarcor.github.io/osvb/index.html + https://www.linkedin.com/pulse/1932021-python-now-replaces-tcl-all-besteda-apis-avidan-efody/ + “TCL has served us well, over the years, allowing us to provide an API, and at the same time ensure nobody will ever use it. I will miss it”. + https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/comb-full-adder.html + https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/carry4.html + FuseSoC is used by MicroWatt and Western Digital cores + OpenTitan also uses FuseSoC + LowRISC is UK based + https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/ +```