X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=resources.mdwn;h=a94af724643e3462774e61b14f5524e4a0a150d7;hb=f5797af2c9b718cf73b7fd50e7e3abfceff6585a;hp=ba7e0843169d37ac1083cc3558d5e6b73e658317;hpb=e01aa4488195f8569653fc8c4b487d2801792cf5;p=libreriscv.git diff --git a/resources.mdwn b/resources.mdwn index ba7e08431..a94af7246 100644 --- a/resources.mdwn +++ b/resources.mdwn @@ -4,10 +4,34 @@ This page aims to collect all the resources and specifications we need in one place for quick access. We will try our best to keep links here up-to-date. Feel free to add more links here. +[[!toc ]] + +# Getting Started + +This section is primarily a series of useful links found online + +* [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019) +* Fundamentals to learn to get started [[3d_gpu/tutorial]] + +## Is Open Source Hardware Profitable? +[RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be) + +# OpenPOWER ISA + +* [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0) +* [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b) + +## Overview of the user ISA: + +[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425) + # RISC-V Instruction Set Architecture +**PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space +RISCV + The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name -of the project implies, we will be following the RISC-V ISA due to it +of the project implies, we will be following the RISC-V ISA I due to it being open-source and also because of the huge software and hardware ecosystem building around it. There are other open-source ISAs but none of them have the same momentum and energy behind it as RISC-V. @@ -16,19 +40,35 @@ To fully take advantage of the RISC-V ecosystem, it is important to be compliant with the RISC-V standards. Doing so will allow us to to reuse most software as-is and avoid major forks. -* Official compiled PDFs of RISC-V ISA Manual: - -* Working draft of the proposed RISC-V Bitmanipulation extension: - -* RISC-V "V" Vector Extension: - +* [Official compiled PDFs of RISC-V ISA Manual] + (https://github.com/riscv/riscv-isa-manual/releases/latest) +* [Working draft of the proposed RISC-V Bitmanipulation extension](https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf) +* [RISC-V "V" Vector Extension](https://riscv.github.io/documents/riscv-v-spec/) +* [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md) Note: As far as I know, we aren't using the RISC-V V Extension directly at the moment. However, there are many wiki pages that make a reference to the V extension so it would be good to include it here as a reference for comparative/informative purposes with regard to Simple-V. -# IEEE Standard for Floating-Point Arithmetic (IEEE 754) +## Radix MMU + - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182) + + +# RTL Arithmetic SQRT, FPU etc. + +## Sqrt +* [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf) +* [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf) + +## CORDIC and related algorithms +* [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm) +* [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf) + - Does not have an easy way of computing tan(x) +* [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html) +* [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access) + +## IEEE Standard for Floating-Point Arithmetic (IEEE 754) Almost all modern computers follow the IEEE Floating-Point Standard. Of course, we will follow it as well for interoperability. @@ -40,6 +80,12 @@ it is unfortunately not freely available and requires a payment to access. However, each of the Libre RISC-V members already have access to the document. +## Past FPU Mistakes to learn from + +* [Intel Underestimates Error Bounds by 1.3 quintillion on +Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/) +* [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy) + # Khronos Standards The Khronos Group creates open standards for authoring and acceleration @@ -52,28 +98,21 @@ Kazan driver. Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic switching between different accuracy levels, in userspace applications. -**SPIR-V Main Page ** +[**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/) -* SPIR-V 1.5 Specification Revision 1: - -* SPIR-V OpenCL Extended Instruction Set: - -* SPIR-V GLSL Extended Instruction Set: - +* [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html) +* [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html) +* [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html) -**Vulkan Main Page ** +[**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/) -* Vulkan 1.1.122: - +* [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html) -**OpenCL Main Page ** +[**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/) -* OpenCL 2.2 API Specification: - -* OpenCL 2.2 Extension Specification: - -* OpenCL 2.2 SPIR-V Environment Specification: - +* [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html) +* [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html) +* [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html) Note: We are implementing hardware accelerated Vulkan and OpenCL while relying on other software projects to translate APIs to @@ -87,7 +126,25 @@ although performance is not evaluated. -# Free Silicon Conference +# Various POWER Communities + - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/) + The T2080 is a POWER8 chip. + - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/) + Supporting/Raising awareness of various POWER related open projects on the FOSS + community + - [OpenPOWER](https://openpowerfoundation.org) + Promotes and ensure compliance with the Power ISA amongst members. + - [OpenCapi](https://opencapi.org) + High performance interconnect for POWER machines. One of the big advantages + of the POWER architecture. Notably more performant than PCIE Gen4, and is + designed to be layered on top of the physical PCIE link. + - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/) + Truly open bi-weekly teleconference lines for anybody interested in helping + advance or adopting the POWER architecture. + +# Conferences + +## Free Silicon Conference The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and @@ -130,17 +187,22 @@ test. It's still in development as far as I can tell. * //TODO LINK TO RISC-V CONFORMANCE TEST -## IEEE 754 Tests +## IEEE 754 Testing/Emulation + +IEEE 754 has no official tests for floating-point but there are +well-known third party tools to check such as John Hauser's TestFloat. -IEEE 754 has no official tests for floating-point but there are several -well-known third party tools to check such as John Hauser's SoftFloat -and TestFloat. +There is also his SoftFloat library, which is a software emulation +library for IEEE 754. * -Jacob is also making a Rust library to check IEEE 754 operations. +Jacob is also working on an IEEE 754 software emulation library written +in Rust which also has Python bindings: -* +* Source: +* Crate: +* Autogenerated Docs: A cool paper I came across in my research is "IeeeCC754++ : An Advanced Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken. @@ -171,25 +233,104 @@ thousands or millions of silicon. Some learning resources I found in the community: -* ZipCPU: +* ZipCPU: ZipCPU provides a comprehensive + tutorial for beginners and many exercises/quizzes/slides: + +* Western Digital's SweRV CPU blog (I recommend looking at all their + posts): +* +* + +## Automation + +* -ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizzes/slides: +# LLVM +## Adding new instructions: -* Western Digital's SweRV CPU blog (I recommend looking at all their posts): +* - +# Branch Prediction - +* -## Automation +# Python RTL Tools -* +* [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/) +* [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers) + An SOC builder written in Python Migen DSL. Allows you to generate functional + RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support, + and parameterizeable CSRs. +* [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>) +* There is a great guy, Robert Baruch, who has a good + [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen. + He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put + [the code](https://github.com/RobertBaruch/n6800) and + [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw) + online. +* [Minerva](https://github.com/lambdaconcept/minerva) + An SOC written in Python nMigen DSL +* [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html) +* +* + +# Other + +* + +# Real/Physical Projects + +* [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu) +* +* +* +* +* +* +* + +# ASIC tape-out pricing + +* -# Libre-RISC-V Standards +# Funding + +* +* [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02) + +# Good Programming/Design Practices + +* [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle) +* [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment) +* +* [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/) + +* +* +* Fundamentals of Modern VLSI Devices + + +# 12 skills summary + +* + +# Analog Simulation + +* +* +* +* + +# Libre-SOC Standards This list auto-generated from a page tag "standards": [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]] +# Server setup + +* [[resources/server-setup/web-server]] +* [[resources/server-setup/git-mirroring]] +* [[resources/server-setup/nagios-monitoring]]