X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=resources.mdwn;h=ae392ed325510378d61819555406109b358b439a;hb=c13172a0d81708a14668fa4f6ff9854e32bf8b03;hp=7a476ba45c3f37e88d9a7f3ab7352e6a935a59a9;hpb=db02f1ca2bbc8bd661a490c0728533f310be3dbf;p=libreriscv.git
diff --git a/resources.mdwn b/resources.mdwn
index 7a476ba45..ae392ed32 100644
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -23,7 +23,8 @@ This section is primarily a series of useful links found online
## Overview of the user ISA:
-[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* Power ISA listings
## OpenPOWER OpenFSI Spec (2016)
@@ -31,12 +32,26 @@ This section is primarily a series of useful links found online
* [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
+# Energy-efficient cores
+
+* https://arxiv.org/abs/2002.10143
+
# Communities
*
*
*
+* Open tape-out mailing list
+
+# Other GPU Specifications
+*
+* https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf
+* https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf
+* MALI Midgard
+* [Nyuzi](https://github.com/jbush001/NyuziProcessor)
+* VideoCore IV
+* etnaviv
# JTAG
@@ -46,40 +61,18 @@ This section is primarily a series of useful links found online
"The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications."
-# RISC-V Instruction Set Architecture
-
-**PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
-RISCV
-
-The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
-of the project implies, we will be following the RISC-V ISA I due to it
-being open-source and also because of the huge software and hardware
-ecosystem building around it. There are other open-source ISAs but none
-of them have the same momentum and energy behind it as RISC-V.
-
-To fully take advantage of the RISC-V ecosystem, it is important to be
-compliant with the RISC-V standards. Doing so will allow us to to reuse
-most software as-is and avoid major forks.
-
-* [Official compiled PDFs of RISC-V ISA Manual]
- (https://github.com/riscv/riscv-isa-manual/releases/latest)
-* [Working draft of the proposed RISC-V Bitmanipulation extension](https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf)
-* [RISC-V "V" Vector Extension](https://riscv.github.io/documents/riscv-v-spec/)
-* [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
-
-Note: As far as I know, we aren't using the RISC-V V Extension directly
-at the moment (correction: we were never going to). However, there are many wiki pages that make a reference
-to the V extension so it would be good to include it here as a reference
-for comparative/informative purposes with regard to Simple-V.
-
-
# Radix MMU
- [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
# D-Cache
+- [A Primer on Memory Consistency and Cache Coherence
+](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049)
+
## D-Cache Possible Optimizations papers and links
- [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
+- [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
+Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901)
# BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
- [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
@@ -120,7 +113,7 @@ course, we will follow it as well for interoperability.
Note: Even though this is such an important standard used by everyone,
it is unfortunately not freely available and requires a payment to
-access. However, each of the Libre RISC-V members already have access
+access. However, each of the Libre-SOC members already have access
to the document.
* [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
@@ -139,6 +132,7 @@ Random ASCII â tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2
* How not to design an ISA
Meester Forsyth
+
# Khronos Standards
The Khronos Group creates open standards for authoring and acceleration
@@ -176,6 +170,10 @@ Note: We are implementing hardware accelerated Vulkan and
OpenCL while relying on other software projects to translate APIs to
Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
+# Open Source (CC BY + MIT) DirectX specs (by Microsoft, but not official specs)
+
+https://github.com/Microsoft/DirectX-Specs
+
# Graphics and Compute API Stack
I found this informative post that mentions Kazan and a whole bunch of
@@ -212,14 +210,10 @@ although performance is not evaluated.
# Conferences
-## Free Silicon Conference
+see [[conferences]]
-The conference brought together experts and enthusiasts who want to build
-a complete Free and Open Source CAD ecosystem for designing analog and
-digital integrated circuits. The conference covered the full spectrum of
-the design process, from system architecture, to layout and verification.
-*
+# Coriolis2
* LIP6's Coriolis - a set of backend design tools:
@@ -227,8 +221,19 @@ the design process, from system architecture, to layout and verification.
Note: The rest of LIP6's website is in French, but there is a UK flag
in the corner that gives the English version.
+# Logical Equivalence and extraction
+
+* NETGEN
+* CVC https://github.com/d-m-bailey/cvc
+
+# Klayout
+
* KLayout - Layout viewer and editor:
+# image to GDS-II
+
+* https://nazca-design.org/convert-image-to-gds/
+
# The OpenROAD Project
OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
@@ -302,6 +307,8 @@ thousands or millions of silicon.
* Possible way to speed up our solvers for our formal proofs
* Algorithms (papers) submitted for 2018 International SAT Competition
+* Minisail - compiler
+ for SAIL into c
Some learning resources I found in the community:
@@ -317,6 +324,18 @@ Some learning resources I found in the community:
*
+# Bus Architectures
+
+* Avalon
+* CXM
+
+# Vector Processors
+
+* THOR
+* NEC SX-Aurora
+* RVV
+* MRISC32
+
# LLVM
## Adding new instructions:
@@ -341,13 +360,13 @@ Some learning resources I found in the community:
[the code](https://github.com/RobertBaruch/n6800) and
[instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
online.
+ There is now a page [[docs/learning_nmigen]].
* [Minerva](https://github.com/lambdaconcept/minerva)
An SOC written in Python nMigen DSL
* Minerva example using nmigen-soc
* [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
*
-*
# Other
@@ -358,6 +377,7 @@ Some learning resources I found in the community:
*
* pipeline skid buffer
* GTKwave
+* - Waveform Analysis
*
Synchronous Resets? Asynchronous Resets? I am so confused! How will I
ever know which to use? by Clifford E. Cummings
@@ -369,6 +389,8 @@ Some learning resources I found in the community:
*
Understanding Latency Hiding on GPUs, by Vasily Volkov
* Efabless "Openlane"
+* example of openlane with nmigen
+
* Co-simulation plugin for verilator, transferring to ECP5
* Multi-read/write ported memories
@@ -383,6 +405,7 @@ Some learning resources I found in the community:
* Circuitverse 16-bit
* Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
+
# Real/Physical Projects
* [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)