X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=resources.mdwn;h=ba7e0843169d37ac1083cc3558d5e6b73e658317;hb=432fc8fa41d0b4959676c4915e04f7c79a9bdce6;hp=6a4d133a3008f6edc39b751eb64acf7dc7e9175d;hpb=55f4ef09a7fadc95c4d11f6be4937221460eea77;p=libreriscv.git diff --git a/resources.mdwn b/resources.mdwn index 6a4d133a3..ba7e08431 100644 --- a/resources.mdwn +++ b/resources.mdwn @@ -1,23 +1,195 @@ -# This page aims to collect all the resources and specifications we need in one place for quick access. +# Resources and Specifications -We will try our best to keep links here up-to-date. Feel free to add more links here. +This page aims to collect all the resources and specifications we need +in one place for quick access. We will try our best to keep links here +up-to-date. Feel free to add more links here. # RISC-V Instruction Set Architecture -The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name of the project implies, we will be following the RISC-V ISA due to it being open-source and also because of the huge software and hardware ecosystem building around it. There are other open-source ISAs but none of them have the same momentum and energy behind it as RISC-V. +The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name +of the project implies, we will be following the RISC-V ISA due to it +being open-source and also because of the huge software and hardware +ecosystem building around it. There are other open-source ISAs but none +of them have the same momentum and energy behind it as RISC-V. -To fully take advantage of the RISC-V ecosystem, it is important to be compliant with the RISC-V standards. Doing so will allow us to to reuse most software as-is and avoid major forks. +To fully take advantage of the RISC-V ecosystem, it is important to be +compliant with the RISC-V standards. Doing so will allow us to to reuse +most software as-is and avoid major forks. -* Official compiled PDFs of RISC-V ISA Manual: -* Working draft of the proposed RISC-V Bitmanipulation extension: -* RISC-V "V" Vector Extension: +* Official compiled PDFs of RISC-V ISA Manual: + +* Working draft of the proposed RISC-V Bitmanipulation extension: + +* RISC-V "V" Vector Extension: + -Note: As far as I know, we aren't using the RISC-V V Extension directly at the moment. But, I am putting it here for informative comparison purposes to our own vector extension called SV. +Note: As far as I know, we aren't using the RISC-V V Extension directly +at the moment. However, there are many wiki pages that make a reference +to the V extension so it would be good to include it here as a reference +for comparative/informative purposes with regard to Simple-V. # IEEE Standard for Floating-Point Arithmetic (IEEE 754) -Almost all modern computers follow the IEEE Floating-Point Standard. Of course, we will follow it as well for interoperability. +Almost all modern computers follow the IEEE Floating-Point Standard. Of +course, we will follow it as well for interoperability. + +* IEEE 754-2019: + +Note: Even though this is such an important standard used by everyone, +it is unfortunately not freely available and requires a payment to +access. However, each of the Libre RISC-V members already have access +to the document. + +# Khronos Standards + +The Khronos Group creates open standards for authoring and acceleration +of graphics, media, and computation. It is a requirement for our hybrid +CPU/GPU to be compliant with these standards *as well* as with IEEE754, +in order to be commercially-competitive in both areas: especially Vulkan +and OpenCL being the most important. SPIR-V is also important for the +Kazan driver. + +Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic +switching between different accuracy levels, in userspace applications. + +**SPIR-V Main Page ** + +* SPIR-V 1.5 Specification Revision 1: + +* SPIR-V OpenCL Extended Instruction Set: + +* SPIR-V GLSL Extended Instruction Set: + + +**Vulkan Main Page ** + +* Vulkan 1.1.122: + + +**OpenCL Main Page ** + +* OpenCL 2.2 API Specification: + +* OpenCL 2.2 Extension Specification: + +* OpenCL 2.2 SPIR-V Environment Specification: + + +Note: We are implementing hardware accelerated Vulkan and +OpenCL while relying on other software projects to translate APIs to +Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software. + +# Graphics and Compute API Stack + +I found this informative post that mentions Kazan and a whole bunch of +other stuff. It looks like *many* APIs can be emulated on top of Vulkan, +although performance is not evaluated. + + + +# Free Silicon Conference + +The conference brought together experts and enthusiasts who want to build +a complete Free and Open Source CAD ecosystem for designing analog and +digital integrated circuits. The conference covered the full spectrum of +the design process, from system architecture, to layout and verification. + +* + +* LIP6's Coriolis - a set of backend design tools: + + +Note: The rest of LIP6's website is in French, but there is a UK flag +in the corner that gives the English version. + +* KLayout - Layout viewer and editor: + +# The OpenROAD Project + +OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source +layout generation flow (RTL-to-GDS). + +* + +# Other RISC-V GPU attempts + +* + +* + +* + +TODO: Get in touch and discuss collaboration + +# Tests, Benchmarks, Conformance, Compliance, Verification, etc. + +## RISC-V Tests + +RISC-V Foundation is in the process of creating an official conformance +test. It's still in development as far as I can tell. + +* //TODO LINK TO RISC-V CONFORMANCE TEST + +## IEEE 754 Tests + +IEEE 754 has no official tests for floating-point but there are several +well-known third party tools to check such as John Hauser's SoftFloat +and TestFloat. + +* + +Jacob is also making a Rust library to check IEEE 754 operations. + +* + +A cool paper I came across in my research is "IeeeCC754++ : An Advanced +Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken. + +* Direct link to PDF: + + +## Khronos Tests + +OpenCL Conformance Tests + +* + +Vulkan Conformance Tests + +* + +MAJOR NOTE: We are **not** allowed to say we are compliant with any of +the Khronos standards until we actually make an official submission, +do the paperwork, and pay the relevant fees. + +## Formal Verification + +Formal verification of Libre RISC-V ensures that it is bug-free in +regards to what we specify. Of course, it is important to do the formal +verification as a final step in the development process before we produce +thousands or millions of silicon. + +Some learning resources I found in the community: + +* ZipCPU: + +ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizzes/slides: + + +* Western Digital's SweRV CPU blog (I recommend looking at all their posts): + + + + + +## Automation + +* + +# Libre-RISC-V Standards + +This list auto-generated from a page tag "standards": + +[[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]] -* -Note: Even though this is such an important standard used by everyone, it is unfortunately not freely available and requires a payment to access. However, each of the Libre RISC-V members already have access to the document.