X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=resources.mdwn;h=d546db17145281fd8c51b60148df414bf4dc38e9;hb=474c45a232daacc3e2c9dc9acc553415ee38fc61;hp=258366a431d2b761a12ba429189302f0c87f28e2;hpb=224d31492894ddcd594b75d5d11206ab74d48e3f;p=libreriscv.git diff --git a/resources.mdwn b/resources.mdwn index 258366a43..d546db171 100644 --- a/resources.mdwn +++ b/resources.mdwn @@ -20,10 +20,14 @@ This section is primarily a series of useful links found online * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0) * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b) +* Virginia Tech course +* mini functional simulator https://github.com/god-s-perfect-idiot/POWER-sim +* https://raw.githubusercontent.com/linuxppc/public-docs/main/ISA/PowerPC_Assembly_IBM_Programming_Environment_2.3.pdf ## Overview of the user ISA: -[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425) +* [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425) +* Power ISA listings ## OpenPOWER OpenFSI Spec (2016) @@ -31,11 +35,32 @@ This section is primarily a series of useful links found online * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf) +# Energy-efficient cores + +* https://arxiv.org/abs/2002.10143 +* https://arxiv.org/abs/2011.08070 + +# Open Access Publication locations + +* + # Communities * * * +* Open tape-out mailing list + +# ppc64 ELF ABI + +* EABI 1.9 supplement +* https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.pdf +* v2.1.5 + +# Similar concepts + +* Vector registers may be + made "ultra-wide" (SX Aurora / Cray) # Other GPU Specifications @@ -43,10 +68,25 @@ This section is primarily a series of useful links found online * https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf * https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf * MALI Midgard -* Nyuzi +* [Nyuzi](https://github.com/jbush001/NyuziProcessor) * VideoCore IV * etnaviv +# Other CPUs and ISAs worth considering + +* https://en.m.wikipedia.org/wiki/Zilog_Z380 +* Mitch Alsup 66000 +* Hitachi Sh2 + https://lists.j-core.org/pipermail/j-core/ + http://shared-ptr.com/sh_insns.html +* 68080 except Length-Decode is a pig for Multi-Issue + http://www.apollo-core.com/index.htm?page=coding&tl=1 + +# Package Management + +* +* + # JTAG * [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf) @@ -60,8 +100,13 @@ This section is primarily a series of useful links found online # D-Cache +- [A Primer on Memory Consistency and Cache Coherence +](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049) + ## D-Cache Possible Optimizations papers and links - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093) +- [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of +Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901) # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s) @@ -210,6 +255,11 @@ see [[conferences]] Note: The rest of LIP6's website is in French, but there is a UK flag in the corner that gives the English version. +# Logical Equivalence and extraction + +* NETGEN +* CVC https://github.com/d-m-bailey/cvc + # Klayout * KLayout - Layout viewer and editor: @@ -304,10 +354,31 @@ Some learning resources I found in the community: * * +VAMP CPU + +* Formal verification of a fully IEEE compliant floating point unit + +* +* the PVS/hw subfolder is under the 2-clause BSD license: + +* + ## Automation * +# Bus Architectures + +* Avalon +* CXM + +# Vector Processors + +* THOR +* NEC SX-Aurora +* RVV +* MRISC32 + # LLVM ## Adding new instructions: @@ -320,11 +391,9 @@ Some learning resources I found in the community: # Python RTL Tools +* pylog fpga + * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/) -* [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers) - An SOC builder written in Python Migen DSL. Allows you to generate functional - RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support, - and parameterizeable CSRs. * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>) * There is a great guy, Robert Baruch, who has a good [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen. @@ -333,16 +402,17 @@ Some learning resources I found in the community: [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw) online. There is now a page [[docs/learning_nmigen]]. -* [Minerva](https://github.com/lambdaconcept/minerva) - An SOC written in Python nMigen DSL -* Minerva example using nmigen-soc - * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html) * -* # Other +* 10-bit SAR ADC +* Cray-1 Pocket Reference + + + +* Prefix-tree generation scripts * N1 * Libre Cell Library * @@ -350,6 +420,8 @@ Some learning resources I found in the community: * * pipeline skid buffer * GTKwave +* - console-based vcd viewer +* - Waveform Analysis * Synchronous Resets? Asynchronous Resets? I am so confused! How will I ever know which to use? by Clifford E. Cummings @@ -376,7 +448,9 @@ Some learning resources I found in the community: * Circuit of Compunit * Circuitverse 16-bit * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance. - + +* adrian_b architecture comparison +* ericandecscent RISC-V # Real/Physical Projects @@ -403,7 +477,7 @@ Some learning resources I found in the community: * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle) * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment) * -* [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/) +* [It's not a zero-sum game](https://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/) * * @@ -484,9 +558,20 @@ This list auto-generated from a page tag "standards": * * +# Handy Compiler Algorithms for SimpleV + +Requires aligned registers: + +* [Graph Coloring Register Allocation for Processors with Multi-Register Operands](https://dl.acm.org/doi/pdf/10.1145/93548.93552) + +More general: + +* [Retargetable Graph-Coloring Register Allocation for Irregular Architectures](https://user.it.uu.se/~svenolof/wpo/AllocSCOPES2003.20030626b.pdf) + # TODO investigate ``` + https://www.nextplatform.com/2022/08/22/the-expanding-cxl-memory-hierarchy-is-inevitable-and-good-enough/ https://github.com/idea-fasoc/OpenFASOC https://www.quicklogic.com/2020/06/18/the-tipping-point/ https://www.quicklogic.com/blog/ @@ -508,4 +593,8 @@ This list auto-generated from a page tag "standards": OpenTitan also uses FuseSoC LowRISC is UK based https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/ + https://cirosantilli.com/x86-paging + https://stackoverflow.com/questions/18431261/how-does-x86-paging-work + http://denninginstitute.com/modules/vm/red/i486page.html + https://m.slashdot.org/story/391021 - mirror neural atrophy results in destruction of empathy ```