X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=resources.mdwn;h=d546db17145281fd8c51b60148df414bf4dc38e9;hb=62918721dc0acd36c5913e02aaf657dd1150f4b2;hp=6c5a54bb17c26f8616b85598e2a96cf8e2a03709;hpb=8a289515cb7bb31613f7116cb08d96ea501f46dd;p=libreriscv.git diff --git a/resources.mdwn b/resources.mdwn index 6c5a54bb1..d546db171 100644 --- a/resources.mdwn +++ b/resources.mdwn @@ -20,10 +20,14 @@ This section is primarily a series of useful links found online * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0) * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b) +* Virginia Tech course +* mini functional simulator https://github.com/god-s-perfect-idiot/POWER-sim +* https://raw.githubusercontent.com/linuxppc/public-docs/main/ISA/PowerPC_Assembly_IBM_Programming_Environment_2.3.pdf ## Overview of the user ISA: -[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425) +* [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425) +* Power ISA listings ## OpenPOWER OpenFSI Spec (2016) @@ -31,55 +35,78 @@ This section is primarily a series of useful links found online * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf) +# Energy-efficient cores + +* https://arxiv.org/abs/2002.10143 +* https://arxiv.org/abs/2011.08070 + +# Open Access Publication locations + +* + # Communities * * * +* Open tape-out mailing list +# ppc64 ELF ABI -# JTAG +* EABI 1.9 supplement +* https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.pdf +* v2.1.5 -* [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf) +# Similar concepts - Abstract +* Vector registers may be + made "ultra-wide" (SX Aurora / Cray) - "The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications." +# Other GPU Specifications -# RISC-V Instruction Set Architecture +* +* https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf +* https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf +* MALI Midgard +* [Nyuzi](https://github.com/jbush001/NyuziProcessor) +* VideoCore IV +* etnaviv -**PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space -RISCV +# Other CPUs and ISAs worth considering -The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name -of the project implies, we will be following the RISC-V ISA I due to it -being open-source and also because of the huge software and hardware -ecosystem building around it. There are other open-source ISAs but none -of them have the same momentum and energy behind it as RISC-V. +* https://en.m.wikipedia.org/wiki/Zilog_Z380 +* Mitch Alsup 66000 +* Hitachi Sh2 + https://lists.j-core.org/pipermail/j-core/ + http://shared-ptr.com/sh_insns.html +* 68080 except Length-Decode is a pig for Multi-Issue + http://www.apollo-core.com/index.htm?page=coding&tl=1 -To fully take advantage of the RISC-V ecosystem, it is important to be -compliant with the RISC-V standards. Doing so will allow us to to reuse -most software as-is and avoid major forks. +# Package Management -* [Official compiled PDFs of RISC-V ISA Manual] - (https://github.com/riscv/riscv-isa-manual/releases/latest) -* [Working draft of the proposed RISC-V Bitmanipulation extension](https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf) -* [RISC-V "V" Vector Extension](https://riscv.github.io/documents/riscv-v-spec/) -* [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md) +* +* -Note: As far as I know, we aren't using the RISC-V V Extension directly -at the moment (correction: we were never going to). However, there are many wiki pages that make a reference -to the V extension so it would be good to include it here as a reference -for comparative/informative purposes with regard to Simple-V. - +# JTAG + +* [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf) + + Abstract + + "The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications." # Radix MMU - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182) # D-Cache +- [A Primer on Memory Consistency and Cache Coherence +](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049) + ## D-Cache Possible Optimizations papers and links - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093) +- [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of +Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901) # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s) @@ -120,7 +147,7 @@ course, we will follow it as well for interoperability. Note: Even though this is such an important standard used by everyone, it is unfortunately not freely available and requires a payment to -access. However, each of the Libre RISC-V members already have access +access. However, each of the Libre-SOC members already have access to the document. * [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html) @@ -139,6 +166,7 @@ Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2 * How not to design an ISA Meester Forsyth + # Khronos Standards The Khronos Group creates open standards for authoring and acceleration @@ -176,6 +204,10 @@ Note: We are implementing hardware accelerated Vulkan and OpenCL while relying on other software projects to translate APIs to Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software. +# Open Source (CC BY + MIT) DirectX specs (by Microsoft, but not official specs) + +https://github.com/Microsoft/DirectX-Specs + # Graphics and Compute API Stack I found this informative post that mentions Kazan and a whole bunch of @@ -212,14 +244,10 @@ although performance is not evaluated. # Conferences -## Free Silicon Conference +see [[conferences]] -The conference brought together experts and enthusiasts who want to build -a complete Free and Open Source CAD ecosystem for designing analog and -digital integrated circuits. The conference covered the full spectrum of -the design process, from system architecture, to layout and verification. -* +# Coriolis2 * LIP6's Coriolis - a set of backend design tools: @@ -227,8 +255,19 @@ the design process, from system architecture, to layout and verification. Note: The rest of LIP6's website is in French, but there is a UK flag in the corner that gives the English version. +# Logical Equivalence and extraction + +* NETGEN +* CVC https://github.com/d-m-bailey/cvc + +# Klayout + * KLayout - Layout viewer and editor: +# image to GDS-II + +* https://nazca-design.org/convert-image-to-gds/ + # The OpenROAD Project OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source @@ -302,6 +341,8 @@ thousands or millions of silicon. * Possible way to speed up our solvers for our formal proofs * Algorithms (papers) submitted for 2018 International SAT Competition +* Minisail - compiler + for SAIL into c Some learning resources I found in the community: @@ -313,10 +354,31 @@ Some learning resources I found in the community: * * +VAMP CPU + +* Formal verification of a fully IEEE compliant floating point unit + +* +* the PVS/hw subfolder is under the 2-clause BSD license: + +* + ## Automation * +# Bus Architectures + +* Avalon +* CXM + +# Vector Processors + +* THOR +* NEC SX-Aurora +* RVV +* MRISC32 + # LLVM ## Adding new instructions: @@ -329,11 +391,9 @@ Some learning resources I found in the community: # Python RTL Tools +* pylog fpga + * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/) -* [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers) - An SOC builder written in Python Migen DSL. Allows you to generate functional - RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support, - and parameterizeable CSRs. * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>) * There is a great guy, Robert Baruch, who has a good [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen. @@ -341,16 +401,18 @@ Some learning resources I found in the community: [the code](https://github.com/RobertBaruch/n6800) and [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw) online. -* [Minerva](https://github.com/lambdaconcept/minerva) - An SOC written in Python nMigen DSL -* Minerva example using nmigen-soc - + There is now a page [[docs/learning_nmigen]]. * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html) * -* # Other +* 10-bit SAR ADC +* Cray-1 Pocket Reference + + + +* Prefix-tree generation scripts * N1 * Libre Cell Library * @@ -358,6 +420,8 @@ Some learning resources I found in the community: * * pipeline skid buffer * GTKwave +* - console-based vcd viewer +* - Waveform Analysis * Synchronous Resets? Asynchronous Resets? I am so confused! How will I ever know which to use? by Clifford E. Cummings @@ -369,6 +433,8 @@ Some learning resources I found in the community: * Understanding Latency Hiding on GPUs, by Vasily Volkov * Efabless "Openlane" +* example of openlane with nmigen + * Co-simulation plugin for verilator, transferring to ECP5 * Multi-read/write ported memories @@ -382,7 +448,10 @@ Some learning resources I found in the community: * Circuit of Compunit * Circuitverse 16-bit * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance. - + +* adrian_b architecture comparison +* ericandecscent RISC-V + # Real/Physical Projects * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu) @@ -408,7 +477,7 @@ Some learning resources I found in the community: * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle) * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment) * -* [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/) +* [It's not a zero-sum game](https://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/) * * @@ -460,6 +529,21 @@ This list auto-generated from a page tag "standards": * [[resources/high-speed-serdes-in-circuitjs]] +# Logic Simulator 2 +* +[Live web version](https://dkilfoyle.github.io/logic2/) + +> ## Features +> 1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr) +> 2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints +> 3. IDE docking ui courtesy of JupyterLab's Lumino widgets +> 4. Schematic visualisation courtesy of d3-hwschematic +> 5. Testbench simulation with graphical trace output and schematic animation +> 6. Circuit description as gates, boolean logic or verilog behavioural model +> 7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map + +[from the GitHub page. As of 2021/03/29] + # ASIC Timing and Design flow resources * @@ -473,3 +557,44 @@ This list auto-generated from a page tag "standards": * * * + +# Handy Compiler Algorithms for SimpleV + +Requires aligned registers: + +* [Graph Coloring Register Allocation for Processors with Multi-Register Operands](https://dl.acm.org/doi/pdf/10.1145/93548.93552) + +More general: + +* [Retargetable Graph-Coloring Register Allocation for Irregular Architectures](https://user.it.uu.se/~svenolof/wpo/AllocSCOPES2003.20030626b.pdf) + +# TODO investigate + +``` + https://www.nextplatform.com/2022/08/22/the-expanding-cxl-memory-hierarchy-is-inevitable-and-good-enough/ + https://github.com/idea-fasoc/OpenFASOC + https://www.quicklogic.com/2020/06/18/the-tipping-point/ + https://www.quicklogic.com/blog/ + https://www.quicklogic.com/2020/09/15/why-open-source-ecosystems-make-good-business-sense/ + https://www.quicklogic.com/qorc/ + https://en.wikipedia.org/wiki/RAD750 + The RAD750 system has a price that is comparable to the RAD6000, the latter of which as of 2002 was listed at US$200,000 (equivalent to $284,292 in 2019). + https://theamphour.com/525-open-fpga-toolchains-and-machine-learning-with-brian-faith-of-quicklogic/ + https://github.blog/2021-03-22-open-innovation-winning-strategy-digital-sovereignty-human-progress/ + https://github.com/olofk/edalize + https://github.com/hdl/containers + https://twitter.com/OlofKindgren/status/1374848733746192394 + You might also want to check out https://umarcor.github.io/osvb/index.html + https://www.linkedin.com/pulse/1932021-python-now-replaces-tcl-all-besteda-apis-avidan-efody/ + “TCL has served us well, over the years, allowing us to provide an API, and at the same time ensure nobody will ever use it. I will miss it”. + https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/comb-full-adder.html + https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/carry4.html + FuseSoC is used by MicroWatt and Western Digital cores + OpenTitan also uses FuseSoC + LowRISC is UK based + https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/ + https://cirosantilli.com/x86-paging + https://stackoverflow.com/questions/18431261/how-does-x86-paging-work + http://denninginstitute.com/modules/vm/red/i486page.html + https://m.slashdot.org/story/391021 - mirror neural atrophy results in destruction of empathy +```