X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fdecode.h;h=061b5b6249271152537fc2a4d299e17b5523c8a0;hb=e83a032060865550e33659a69a86870f9da880b1;hp=3a8b3a490dc836d50d9e91418d853c886664ff6f;hpb=990c6c48098e83584edf5282d119187abae04a4d;p=riscv-isa-sim.git diff --git a/riscv/decode.h b/riscv/decode.h index 3a8b3a4..061b5b6 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -7,6 +7,10 @@ # error spike requires a two''s-complement c++ implementation #endif +#ifdef WORDS_BIGENDIAN +# error spike requires a little-endian host +#endif + #include #include #include @@ -202,9 +206,10 @@ private: } while(0) #define set_pc_and_serialize(x) \ - do { set_pc(x); /* check alignment */ \ + do { reg_t __npc = (x); \ + set_pc(__npc); /* check alignment */ \ npc = PC_SERIALIZE_AFTER; \ - STATE.pc = (x); \ + STATE.pc = __npc; \ } while(0) /* Sentinel PC values to serialize simulator pipeline */ @@ -225,27 +230,17 @@ private: throw trap_illegal_instruction(); \ (which); }) -/* Debug CSRs. These should probably be in encoding.h, but that file is - * automatically generated. */ -/* TODO */ -#include "/media/sf_tnewsome/Synced/SiFive/debug-spec/core_registers.tex.h" -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 -#define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEPPED 4 -#define DCSR_CAUSE_HALT 5 - #define DEBUG_START 0x100 #define DEBUG_ROM_START 0x800 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4) +#define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8) #define DEBUG_ROM_END (DEBUG_ROM_START + debug_rom_raw_len) #define DEBUG_RAM_START 0x400 #define DEBUG_RAM_SIZE 64 #define DEBUG_RAM_END (DEBUG_RAM_START + DEBUG_RAM_SIZE) #define DEBUG_END 0xfff -#define DEBUG_CLEARDEBINT 0x108 -#define DEBUG_SETHALTNOT 0x100 +#define DEBUG_CLEARDEBINT 0x100 +#define DEBUG_SETHALTNOT 0x10c #define DEBUG_SIZE (DEBUG_END - DEBUG_START + 1) #endif