X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fdecode.h;h=061b5b6249271152537fc2a4d299e17b5523c8a0;hb=e83a032060865550e33659a69a86870f9da880b1;hp=4c30e623e9684617b88d7b4dbaa7712de355ef56;hpb=94dc73b7f100270d7a6dff912ea985c9204e3fc1;p=riscv-isa-sim.git diff --git a/riscv/decode.h b/riscv/decode.h index 4c30e62..061b5b6 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1,48 +1,34 @@ +// See LICENSE for license details. + #ifndef _RISCV_DECODE_H #define _RISCV_DECODE_H -#define __STDC_LIMIT_MACROS -#include +#if (-1 != ~0) || ((-1 >> 1) != -1) +# error spike requires a two''s-complement c++ implementation +#endif -#include "config.h" +#ifdef WORDS_BIGENDIAN +# error spike requires a little-endian host +#endif -typedef int int128_t __attribute__((mode(TI))); -typedef unsigned int uint128_t __attribute__((mode(TI))); +#include +#include +#include +#include "encoding.h" +#include "config.h" +#include "common.h" +#include typedef int64_t sreg_t; typedef uint64_t reg_t; typedef uint64_t freg_t; -const int OPCODE_BITS = 7; - -const int XPRID_BITS = 5; -const int NXPR = 1 << XPRID_BITS; - -const int FPR_BITS = 64; -const int FPRID_BITS = 5; -const int NFPR = 1 << FPRID_BITS; - -const int IMM_BITS = 12; -const int IMMLO_BITS = 7; -const int TARGET_BITS = 25; -const int FUNCT_BITS = 3; -const int FUNCTR_BITS = 7; -const int FFUNCT_BITS = 2; -const int RM_BITS = 3; -const int BIGIMM_BITS = 20; -const int BRANCH_ALIGN_BITS = 1; -const int JUMP_ALIGN_BITS = 1; - -#define SR_ET 0x0000000000000001ULL -#define SR_PS 0x0000000000000004ULL -#define SR_S 0x0000000000000008ULL -#define SR_EF 0x0000000000000010ULL -#define SR_UX 0x0000000000000020ULL -#define SR_SX 0x0000000000000040ULL -#define SR_IM 0x000000000000FF00ULL -#define SR_ZERO ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_SX | SR_IM) -#define SR_IM_SHIFT 8 -#define TIMER_IRQ 7 +const int NXPR = 32; +const int NFPR = 32; +const int NCSR = 4096; + +#define X_RA 1 +#define X_SP 2 #define FP_RD_NE 0 #define FP_RD_0 1 @@ -56,7 +42,7 @@ const int JUMP_ALIGN_BITS = 1; #define FPEXC_NX 0x01 #define FPEXC_UF 0x02 #define FPEXC_OF 0x04 -#define FPEXC_DZ 0x02 +#define FPEXC_DZ 0x08 #define FPEXC_NV 0x10 #define FSR_AEXC_SHIFT 0 @@ -67,132 +53,194 @@ const int JUMP_ALIGN_BITS = 1; #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) -#define FSR_ZERO ~(FSR_RD | FSR_AEXC) - -// note: bit fields are in little-endian order -struct itype_t -{ - unsigned opcode : OPCODE_BITS; - unsigned funct : FUNCT_BITS; - signed imm12 : IMM_BITS; - unsigned rs1 : XPRID_BITS; - unsigned rd : XPRID_BITS; -}; - -struct btype_t -{ - unsigned opcode : OPCODE_BITS; - unsigned funct : FUNCT_BITS; - unsigned immlo : IMMLO_BITS; - unsigned rs2 : XPRID_BITS; - unsigned rs1 : XPRID_BITS; - signed immhi : IMM_BITS-IMMLO_BITS; -}; - -struct jtype_t -{ - unsigned jump_opcode : OPCODE_BITS; - signed target : TARGET_BITS; -}; - -struct rtype_t -{ - unsigned opcode : OPCODE_BITS; - unsigned funct : FUNCT_BITS; - unsigned functr : FUNCTR_BITS; - unsigned rs2 : XPRID_BITS; - unsigned rs1 : XPRID_BITS; - unsigned rd : XPRID_BITS; -}; - -struct ltype_t -{ - unsigned opcode : OPCODE_BITS; - unsigned bigimm : BIGIMM_BITS; - unsigned rd : XPRID_BITS; -}; +#define insn_length(x) \ + (((x) & 0x03) < 0x03 ? 2 : \ + ((x) & 0x1f) < 0x1f ? 4 : \ + ((x) & 0x3f) < 0x3f ? 6 : \ + 8) +#define MAX_INSN_LENGTH 8 +#define PC_ALIGN 2 -struct ftype_t +typedef uint64_t insn_bits_t; +class insn_t { - unsigned opcode : OPCODE_BITS; - unsigned ffunct : FFUNCT_BITS; - unsigned rm : RM_BITS; - unsigned rs3 : FPRID_BITS; - unsigned rs2 : FPRID_BITS; - unsigned rs1 : FPRID_BITS; - unsigned rd : FPRID_BITS; -}; - -union insn_t -{ - itype_t itype; - jtype_t jtype; - rtype_t rtype; - btype_t btype; - ltype_t ltype; - ftype_t ftype; - uint32_t bits; +public: + insn_t() = default; + insn_t(insn_bits_t bits) : b(bits) {} + insn_bits_t bits() { return b; } + int length() { return insn_length(b); } + int64_t i_imm() { return int64_t(b) >> 20; } + int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); } + int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); } + int64_t u_imm() { return int64_t(b) >> 12 << 12; } + int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); } + uint64_t rd() { return x(7, 5); } + uint64_t rs1() { return x(15, 5); } + uint64_t rs2() { return x(20, 5); } + uint64_t rs3() { return x(27, 5); } + uint64_t rm() { return x(12, 3); } + uint64_t csr() { return x(20, 12); } + + int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); } + int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); } + int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); } + int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); } + int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); } + int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); } + int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); } + int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); } + int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); } + int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); } + int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); } + int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); } + int64_t rvc_simm3() { return x(10, 3); } + uint64_t rvc_rd() { return rd(); } + uint64_t rvc_rs1() { return rd(); } + uint64_t rvc_rs2() { return x(2, 5); } + uint64_t rvc_rs1s() { return 8 + x(7, 3); } + uint64_t rvc_rs2s() { return 8 + x(2, 3); } +private: + insn_bits_t b; + uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); } + uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); } + uint64_t imm_sign() { return xs(63, 1); } }; -#if 0 -#include -class trace_writeback +template +class regfile_t { public: - trace_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {} - - reg_t operator = (reg_t rhs) + void write(size_t i, T value) { - printf("R[%x] <= %llx\n",rd,(long long)rhs); - rf[rd] = rhs; - return rhs; + if (!zero_reg || i != 0) + data[i] = value; + } + const T& operator [] (size_t i) const + { + return data[i]; } - private: - reg_t* rf; - int rd; + T data[N]; }; -#define do_writeback(rf,rd) trace_writeback(rf,rd) +// helpful macros, etc +#define MMU (*p->get_mmu()) +#define STATE (*p->get_state()) +#define READ_REG(reg) STATE.XPR[reg] +#define READ_FREG(reg) STATE.FPR[reg] +#define RS1 READ_REG(insn.rs1()) +#define RS2 READ_REG(insn.rs2()) +#define WRITE_RD(value) WRITE_REG(insn.rd(), value) + +#ifndef RISCV_ENABLE_COMMITLOG +# define WRITE_REG(reg, value) STATE.XPR.write(reg, value) +# define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, value) #else -#define do_writeback(rf,rd) rf[rd] +# define WRITE_REG(reg, value) ({ \ + reg_t wdata = (value); /* value may have side effects */ \ + STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, wdata}; \ + STATE.XPR.write(reg, wdata); \ + }) +# define WRITE_FREG(reg, value) ({ \ + freg_t wdata = (value); /* value may have side effects */ \ + STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \ + DO_WRITE_FREG(reg, wdata); \ + }) #endif -// helpful macros, etc -#define RS1 XPR[insn.rtype.rs1] -#define RS2 XPR[insn.rtype.rs2] -#define RD do_writeback(XPR,insn.rtype.rd) -#define RA do_writeback(XPR,1) -#define FRS1 FPR[insn.ftype.rs1] -#define FRS2 FPR[insn.ftype.rs2] -#define FRS3 FPR[insn.ftype.rs3] -#define FRD FPR[insn.ftype.rd] -#define BIGIMM insn.ltype.bigimm -#define SIMM insn.itype.imm12 -#define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS)) -#define SHAMT (insn.itype.imm12 & 0x3F) -#define SHAMTW (insn.itype.imm12 & 0x1F) -#define TARGET insn.jtype.target -#define BRANCH_TARGET (npc + (BIMM << BRANCH_ALIGN_BITS)) -#define JUMP_TARGET (npc + (TARGET << JUMP_ALIGN_BITS)) -#define RM ((insn.ftype.rm != 7) ? insn.ftype.rm : \ - ((fsr & FSR_RD) >> FSR_RD_SHIFT)) - -#define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction -#define xpr64 (xprlen == 64) -#define require_xpr64 if(!xpr64) throw trap_illegal_instruction -#define require_xpr32 if(xpr64) throw trap_illegal_instruction -#define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled -#define cmp_trunc(reg) (reg_t(reg) << (64-xprlen)) -#define set_fp_exceptions ({ set_fsr(fsr | \ - (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \ +// RVC macros +#define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value) +#define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value) +#define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value) +#define RVC_RS1 READ_REG(insn.rvc_rs1()) +#define RVC_RS2 READ_REG(insn.rvc_rs2()) +#define RVC_RS1S READ_REG(insn.rvc_rs1s()) +#define RVC_RS2S READ_REG(insn.rvc_rs2s()) +#define RVC_FRS2 READ_FREG(insn.rvc_rs2()) +#define RVC_FRS2S READ_FREG(insn.rvc_rs2s()) +#define RVC_SP READ_REG(X_SP) + +// FPU macros +#define FRS1 READ_FREG(insn.rs1()) +#define FRS2 READ_FREG(insn.rs2()) +#define FRS3 READ_FREG(insn.rs3()) +#define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD)) +#define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD)) +#define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state) +#define WRITE_FRD(value) WRITE_FREG(insn.rd(), value) + +#define SHAMT (insn.i_imm() & 0x3F) +#define BRANCH_TARGET (pc + insn.sb_imm()) +#define JUMP_TARGET (pc + insn.uj_imm()) +#define RM ({ int rm = insn.rm(); \ + if(rm == 7) rm = STATE.frm; \ + if(rm > 4) throw trap_illegal_instruction(); \ + rm; }) + +#define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1))) +#define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask))) + +#define require(x) if (unlikely(!(x))) throw trap_illegal_instruction() +#define require_privilege(p) require(STATE.prv >= (p)) +#define require_rv64 require(xlen == 64) +#define require_rv32 require(xlen == 32) +#define require_extension(s) require(p->supports_extension(s)) +#define require_fp require((STATE.mstatus & MSTATUS_FS) != 0) +#define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0) + +#define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \ + dirty_fp_state; \ + STATE.fflags |= softfloat_exceptionFlags; \ + } \ softfloat_exceptionFlags = 0; }) -static inline sreg_t sext32(int32_t arg) -{ - return arg; -} - -#define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen)) +#define sext32(x) ((sreg_t)(int32_t)(x)) +#define zext32(x) ((reg_t)(uint32_t)(x)) +#define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen)) +#define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen)) + +#define set_pc(x) \ + do { if (unlikely(((x) & 2)) && !p->supports_extension('C')) \ + throw trap_instruction_address_misaligned(x); \ + npc = sext_xlen(x); \ + } while(0) + +#define set_pc_and_serialize(x) \ + do { reg_t __npc = (x); \ + set_pc(__npc); /* check alignment */ \ + npc = PC_SERIALIZE_AFTER; \ + STATE.pc = __npc; \ + } while(0) + +/* Sentinel PC values to serialize simulator pipeline */ +#define PC_SERIALIZE_BEFORE 3 +#define PC_SERIALIZE_AFTER 5 +#define invalid_pc(pc) ((pc) & 1) + +/* Convenience wrappers to simplify softfloat code sequences */ +#define f32(x) ((float32_t){(uint32_t)x}) +#define f64(x) ((float64_t){(uint64_t)x}) + +#define validate_csr(which, write) ({ \ + if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \ + STATE.serialized = false; \ + unsigned csr_priv = get_field((which), 0x300); \ + unsigned csr_read_only = get_field((which), 0xC00) == 3; \ + if (((write) && csr_read_only) || STATE.prv < csr_priv) \ + throw trap_illegal_instruction(); \ + (which); }) + +#define DEBUG_START 0x100 +#define DEBUG_ROM_START 0x800 +#define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4) +#define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8) +#define DEBUG_ROM_END (DEBUG_ROM_START + debug_rom_raw_len) +#define DEBUG_RAM_START 0x400 +#define DEBUG_RAM_SIZE 64 +#define DEBUG_RAM_END (DEBUG_RAM_START + DEBUG_RAM_SIZE) +#define DEBUG_END 0xfff +#define DEBUG_CLEARDEBINT 0x100 +#define DEBUG_SETHALTNOT 0x10c +#define DEBUG_SIZE (DEBUG_END - DEBUG_START + 1) #endif