X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fgdbserver.cc;h=920cb8f833490fa6db8ca85fd9f7e3c25babc52c;hb=71f64bfe4eb2d4d1b0795b71db555fd825593ab3;hp=c4e0fefad11b68f54e0e49df68dfe68d43438864;hpb=9e3b7bdc5ab045e2a526bbbbbb26475b6ef91468;p=riscv-isa-sim.git

diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc
index c4e0fef..920cb8f 100644
--- a/riscv/gdbserver.cc
+++ b/riscv/gdbserver.cc
@@ -1820,8 +1820,6 @@ void gdbserver_t::handle_register_write(const std::vector<uint8_t> &packet)
   processor_t *p = sim->get_core(0);
 
   add_operation(new register_write_op_t(*this, n, value));
-
-  return send_packet("OK");
 }
 
 void gdbserver_t::handle_memory_read(const std::vector<uint8_t> &packet)