X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Fc_flw.h;h=682566c705b764366f4681b6eff3dd85a2c27efa;hb=d6fce459767509249311a120fddb21c844dc9b2c;hp=cdb7221dd47fc0aa4214102ea005e88b08588466;hpb=d5518cd4d9804498204ce8e79ac04870f383966e;p=riscv-isa-sim.git

diff --git a/riscv/insns/c_flw.h b/riscv/insns/c_flw.h
index cdb7221..682566c 100644
--- a/riscv/insns/c_flw.h
+++ b/riscv/insns/c_flw.h
@@ -1,3 +1,8 @@
-require_rvc;
-require_fp;
-FCRDS = mmu.load_int32(CRS1S+CIMM5*4);
+require_extension('C');
+if (xlen == 32) {
+  require_extension('F');
+  require_fp;
+  WRITE_RVC_FRS2S(f32(MMU.load_uint32(RVC_RS1S + insn.rvc_lw_imm())));
+} else { // c.ld
+  WRITE_RVC_RS2S(MMU.load_int64(RVC_RS1S + insn.rvc_ld_imm()));
+}