X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Fc_lwsp.h;fp=riscv%2Finsns%2Fc_lwsp.h;h=ed4dcf30887e4e299fd2cff5835a4faf521dc3e5;hb=d336aee08ba9c5715d5d7836a39003e62ee4ada8;hp=b3d74dbf087fb09553ca438bf4c44629ecfdc032;hpb=d2e9a109e8f7b851fd153b469cc42a8519d85679;p=riscv-isa-sim.git

diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h
index b3d74db..ed4dcf3 100644
--- a/riscv/insns/c_lwsp.h
+++ b/riscv/insns/c_lwsp.h
@@ -1,3 +1,2 @@
 require_extension('C');
-require(insn.rvc_rd() != 0);
 WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));