X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Fsc_d.h;fp=riscv%2Finsns%2Fsc_d.h;h=aeeabd350d36e0c98e2c76bf02dc8adc1f87905b;hb=95487c248a6eb660b9bd1aa49e28da5a1ab21059;hp=01a45ce9094af383e151d039863e8de6df42d9e3;hpb=cc50a327a552f1aa84679c8d3020ec40edc2948f;p=riscv-isa-sim.git

diff --git a/riscv/insns/sc_d.h b/riscv/insns/sc_d.h
index 01a45ce..aeeabd3 100644
--- a/riscv/insns/sc_d.h
+++ b/riscv/insns/sc_d.h
@@ -1,9 +1,11 @@
 require_extension('A');
 require_rv64;
-if (RS1 == p->get_state()->load_reservation)
+if (MMU.check_load_reservation(RS1))
 {
   MMU.store_uint64(RS1, RS2);
   WRITE_RD(0);
 }
 else
   WRITE_RD(1);
+
+MMU.yield_load_reservation();