X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fmmu.cc;h=8df38e5e9d2ebf1a1ce352bf193441f1dab64fac;hb=a80c695b1961ac40086494920f82e85a085ff358;hp=0b28f2ff803be0f0eeb6ef9b6a1e3465463950da;hpb=ee80f2851aef29f8744b5a73afe45a1927c82b37;p=riscv-isa-sim.git

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 0b28f2f..8df38e5 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -180,7 +180,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
     // check that physical address of PTE is legal
     reg_t pte_addr = base + idx * vm.ptesize;
     if (!sim->addr_is_mem(pte_addr))
-      break;
+      throw trap_load_access_fault(addr);
 
     void* ppte = sim->addr_to_mem(pte_addr);
     reg_t pte = vm.ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
@@ -215,9 +215,9 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
 
 fail:
   switch (type) {
-    case FETCH: throw trap_instruction_access_fault(addr);
-    case LOAD: throw trap_load_access_fault(addr);
-    case STORE: throw trap_store_access_fault(addr);
+    case FETCH: throw trap_instruction_page_fault(addr);
+    case LOAD: throw trap_load_page_fault(addr);
+    case STORE: throw trap_store_page_fault(addr);
     default: abort();
   }
 }