X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fmmu.h;fp=riscv%2Fmmu.h;h=715d8397338a10174878df55aff05531e623155b;hb=95487c248a6eb660b9bd1aa49e28da5a1ab21059;hp=4380448f955f73ff4e51f956ad43164076153bec;hpb=cc50a327a552f1aa84679c8d3020ec40edc2948f;p=riscv-isa-sim.git

diff --git a/riscv/mmu.h b/riscv/mmu.h
index 4380448..715d839 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -180,6 +180,29 @@ public:
   amo_func(uint32)
   amo_func(uint64)
 
+  inline void yield_load_reservation()
+  {
+    load_reservation_address = (reg_t)-1;
+  }
+
+  inline void acquire_load_reservation(reg_t vaddr)
+  {
+    reg_t paddr = translate(vaddr, LOAD);
+    if (auto host_addr = sim->addr_to_mem(paddr))
+      load_reservation_address = refill_tlb(vaddr, paddr, host_addr, LOAD).target_offset + vaddr;
+    else
+      throw trap_load_access_fault(vaddr); // disallow LR to I/O space
+  }
+
+  inline bool check_load_reservation(reg_t vaddr)
+  {
+    reg_t paddr = translate(vaddr, STORE);
+    if (auto host_addr = sim->addr_to_mem(paddr))
+      return load_reservation_address == refill_tlb(vaddr, paddr, host_addr, STORE).target_offset + vaddr;
+    else
+      throw trap_store_access_fault(vaddr); // disallow SC to I/O space
+  }
+
   static const reg_t ICACHE_ENTRIES = 1024;
 
   inline size_t icache_index(reg_t addr)
@@ -261,6 +284,7 @@ private:
   simif_t* sim;
   processor_t* proc;
   memtracer_list_t tracer;
+  reg_t load_reservation_address;
   uint16_t fetch_temp;
 
   // implement an instruction cache for simulator performance