X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.cc;fp=riscv%2Fprocessor.cc;h=8bcd8e2cc9dfcf4e0cca5c4fe2d0c5f093815083;hb=b6ec196e9efe33d29d0c9fb80202737719c7730f;hp=ecbe3ef483dc5b15c9102d62498eff2cce12b67b;hpb=8a485de092c1ffc79105db34aca8875203921d63;p=riscv-isa-sim.git

diff --git a/riscv/processor.cc b/riscv/processor.cc
index ecbe3ef..8bcd8e2 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -24,12 +24,16 @@ processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id,
   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
 {
-  disassembler = new disassembler_t(max_xlen);
   parse_isa_string(isa);
   register_base_instructions();
 
   mmu = new mmu_t(sim, this);
 
+  disassembler = new disassembler_t(max_xlen);
+  if (ext)
+    for (auto disasm_insn : ext->get_disasms())
+      disassembler->add_insn(disasm_insn);
+
   reset();
 }