X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.cc;h=064c4520569c2f850ff855561829a66c52d4cdcc;hb=1a623701469c08e72685d44a4ebed9157ab4bfe2;hp=2978ef81a4777380b43576a0dc83bfbfbb4edabe;hpb=e294c392c63b8be738a9493754d302da7e1bb76b;p=riscv-isa-sim.git

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 2978ef8..064c452 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -5,7 +5,7 @@
 #include "common.h"
 #include "config.h"
 #include "sim.h"
-#include "htif.h"
+#include "mmu.h"
 #include "disasm.h"
 #include <cinttypes>
 #include <cmath>
@@ -19,21 +19,18 @@
 #undef STATE
 #define STATE state
 
-processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
-  : sim(sim), ext(NULL), disassembler(new disassembler_t),
-    id(id), run(false), debug(false)
+processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
+        bool halt_on_reset)
+  : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
+  halt_on_reset(halt_on_reset)
 {
   parse_isa_string(isa);
+  register_base_instructions();
 
-  mmu = new mmu_t(sim->mem, sim->memsz);
-  mmu->set_processor(this);
+  mmu = new mmu_t(sim, this);
+  disassembler = new disassembler_t(max_xlen);
 
-  reset(true);
-
-  #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
-  #include "encoding.h"
-  #undef DECLARE_INSN
-  build_opcode_map();
+  reset();
 }
 
 processor_t::~processor_t()
@@ -41,10 +38,9 @@ processor_t::~processor_t()
 #ifdef RISCV_ENABLE_HISTOGRAM
   if (histogram_enabled)
   {
-    fprintf(stderr, "PC Histogram size:%lu\n", pc_histogram.size());
-    for(auto iterator = pc_histogram.begin(); iterator != pc_histogram.end(); ++iterator) {
-      fprintf(stderr, "%0lx %lu\n", (iterator->first << 2), iterator->second);
-    }
+    fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
+    for (auto it : pc_histogram)
+      fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
   }
 #endif
 
@@ -58,57 +54,75 @@ static void bad_isa_string(const char* isa)
   abort();
 }
 
-void processor_t::parse_isa_string(const char* isa)
+void processor_t::parse_isa_string(const char* str)
 {
-  const char* p = isa;
-  const char* all_subsets = "IMAFDC";
+  std::string lowercase, tmp;
+  for (const char *r = str; *r; r++)
+    lowercase += std::tolower(*r);
+
+  const char* p = lowercase.c_str();
+  const char* all_subsets = "imafdc";
 
   max_xlen = 64;
-  cpuid = reg_t(2) << 62;
+  isa = reg_t(2) << 62;
 
-  if (strncmp(p, "RV32", 4) == 0)
-    max_xlen = 32, cpuid = 0, p += 4;
-  else if (strncmp(p, "RV64", 4) == 0)
+  if (strncmp(p, "rv32", 4) == 0)
+    max_xlen = 32, isa = reg_t(1) << 30, p += 4;
+  else if (strncmp(p, "rv64", 4) == 0)
     p += 4;
-  else if (strncmp(p, "RV", 2) == 0)
+  else if (strncmp(p, "rv", 2) == 0)
     p += 2;
 
-  cpuid |= 1L << ('S' - 'A'); // advertise support for supervisor mode
-
-  if (!*p)
+  if (!*p) {
     p = all_subsets;
-  else if (*p != 'I')
-    bad_isa_string(isa);
+  } else if (*p == 'g') { // treat "G" as "IMAFD"
+    tmp = std::string("imafd") + (p+1);
+    p = &tmp[0];
+  } else if (*p != 'i') {
+    bad_isa_string(str);
+  }
+
+  isa_string = "rv" + std::to_string(max_xlen) + p;
+  isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
+  isa |= 1L << ('u' - 'a'); // advertise support for user mode
 
   while (*p) {
-    cpuid |= 1L << (*p - 'A');
+    isa |= 1L << (*p - 'a');
 
     if (auto next = strchr(all_subsets, *p)) {
       all_subsets = next + 1;
       p++;
-    } else if (*p == 'X') {
+    } else if (*p == 'x') {
       const char* ext = p+1, *end = ext;
       while (islower(*end))
         end++;
       register_extension(find_extension(std::string(ext, end - ext).c_str())());
       p = end;
     } else {
-      bad_isa_string(isa);
+      bad_isa_string(str);
     }
   }
 
   if (supports_extension('D') && !supports_extension('F'))
-    bad_isa_string(isa);
+    bad_isa_string(str);
+
+  // advertise support for supervisor and user modes
+  isa |= 1L << ('s' - 'a');
+  isa |= 1L << ('u' - 'a');
+
+  max_isa = isa;
 }
 
 void state_t::reset()
 {
   memset(this, 0, sizeof(*this));
-  mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M);
-  mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_S);
-  mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_S);
-  pc = DEFAULT_MTVEC + 0x100;
+  prv = PRV_M;
+  pc = DEFAULT_RSTVEC;
+  mtvec = DEFAULT_MTVEC;
   load_reservation = -1;
+  tselect = 0;
+  for (unsigned int i = 0; i < num_triggers; i++)
+    mcontrol[i].type = 2;
 }
 
 void processor_t::set_debug(bool value)
@@ -121,15 +135,19 @@ void processor_t::set_debug(bool value)
 void processor_t::set_histogram(bool value)
 {
   histogram_enabled = value;
+#ifndef RISCV_ENABLE_HISTOGRAM
+  if (value) {
+    fprintf(stderr, "PC Histogram support has not been properly enabled;");
+    fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
+  }
+#endif
 }
 
-void processor_t::reset(bool value)
+void processor_t::reset()
 {
-  if (run == !value)
-    return;
-  run = !value;
-
   state.reset();
+  state.dcsr.halt = halt_on_reset;
+  halt_on_reset = false;
   set_csr(CSR_MSTATUS, state.mstatus);
 
   if (ext)
@@ -141,190 +159,113 @@ void processor_t::raise_interrupt(reg_t which)
   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 }
 
-void processor_t::take_interrupt()
+// Count number of contiguous 0 bits starting from the LSB.
+static int ctz(reg_t val)
 {
-  int priv = get_field(state.mstatus, MSTATUS_PRV);
-  int ie = get_field(state.mstatus, MSTATUS_IE);
-  reg_t interrupts = state.mie & state.mip;
-
-  if (priv < PRV_M || (priv == PRV_M && ie)) {
-    if (interrupts & MIP_MSIP)
-      raise_interrupt(IRQ_SOFT);
-
-    if (state.fromhost != 0)
-      raise_interrupt(IRQ_HOST);
-  }
-
-  if (priv < PRV_S || (priv == PRV_S && ie)) {
-    if (interrupts & MIP_SSIP)
-      raise_interrupt(IRQ_SOFT);
-
-    if (interrupts & MIP_STIP)
-      raise_interrupt(IRQ_TIMER);
-  }
+  int res = 0;
+  if (val)
+    while ((val & 1) == 0)
+      val >>= 1, res++;
+  return res;
 }
 
-static void commit_log(state_t* state, reg_t pc, insn_t insn)
+void processor_t::take_interrupt()
 {
-#ifdef RISCV_ENABLE_COMMITLOG
-  if (get_field(state->mstatus, MSTATUS_IE)) {
-    uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
-    if (state->log_reg_write.addr) {
-      fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
-              pc,
-              insn.bits() & mask,
-              state->log_reg_write.addr & 1 ? 'f' : 'x',
-              state->log_reg_write.addr >> 1,
-              state->log_reg_write.data);
-    } else {
-      fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ")\n", pc, insn.bits() & mask);
-    }
-  }
-  state->log_reg_write.addr = 0;
-#endif
-}
+  reg_t pending_interrupts = state.mip & state.mie;
 
-inline void processor_t::update_histogram(size_t pc)
-{
-#ifdef RISCV_ENABLE_HISTOGRAM
-  size_t idx = pc >> 2;
-  pc_histogram[idx]++;
-#endif
-}
+  reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
+  reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
+  reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 
-static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
-{
-  reg_t npc = fetch.func(p, fetch.insn, pc);
-  if (npc != PC_SERIALIZE) {
-    commit_log(p->get_state(), pc, fetch.insn);
-    p->update_histogram(pc);
-  }
-  return npc;
+  reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
+  reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
+  enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
+
+  if (enabled_interrupts)
+    raise_interrupt(ctz(enabled_interrupts));
 }
 
-static void update_timer(state_t* state, size_t instret)
+void processor_t::set_privilege(reg_t prv)
 {
-  uint64_t count0 = (uint64_t)(uint32_t)state->mtime;
-  state->mtime += instret;
-  uint64_t before = count0 - state->stimecmp;
-  if (int64_t(before ^ (before + instret)) < 0)
-    state->mip |= MIP_STIP;
+  assert(prv <= PRV_M);
+  if (prv == PRV_H)
+    prv = PRV_U;
+  mmu->flush_tlb();
+  state.prv = prv;
 }
 
-static size_t next_timer(state_t* state)
+void processor_t::enter_debug_mode(uint8_t cause)
 {
-  return state->stimecmp - (uint32_t)state->mtime;
+  state.dcsr.cause = cause;
+  state.dcsr.prv = state.prv;
+  set_privilege(PRV_M);
+  state.dpc = state.pc;
+  state.pc = debug_rom_entry();
 }
 
-void processor_t::step(size_t n)
+void processor_t::take_trap(trap_t& t, reg_t epc)
 {
-  size_t instret = 0;
-  reg_t pc = state.pc;
-  mmu_t* _mmu = mmu;
-
-  if (unlikely(!run || !n))
-    return;
-  n = std::min(n, next_timer(&state) | 1U);
-
-  #define maybe_serialize() \
-   if (unlikely(pc == PC_SERIALIZE)) { \
-     pc = state.pc; \
-     state.serialized = true; \
-     continue; \
-   }
-
-  try
-  {
-    take_interrupt();
-
-    if (unlikely(debug))
-    {
-      while (instret < n)
-      {
-        insn_fetch_t fetch = mmu->load_insn(pc);
-        if (!state.serialized)
-          disasm(fetch.insn);
-        pc = execute_insn(this, pc, fetch);
-        maybe_serialize();
-        instret++;
-        state.pc = pc;
-      }
-    }
-    else while (instret < n)
-    {
-      size_t idx = _mmu->icache_index(pc);
-      auto ic_entry = _mmu->access_icache(pc);
-
-      #define ICACHE_ACCESS(idx) { \
-        insn_fetch_t fetch = ic_entry->data; \
-        ic_entry++; \
-        pc = execute_insn(this, pc, fetch); \
-        if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
-        if (unlikely(ic_entry->tag != pc)) break; \
-        instret++; \
-        state.pc = pc; \
-      }
-
-      switch (idx) {
-        #include "icache.h"
-      }
+  if (debug) {
+    fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
+            id, t.name(), epc);
+    if (t.has_badaddr())
+      fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
+          t.get_badaddr());
+  }
 
-      maybe_serialize();
-      instret++;
-      state.pc = pc;
+  if (state.dcsr.cause) {
+    if (t.cause() == CAUSE_BREAKPOINT) {
+      state.pc = debug_rom_entry();
+    } else {
+      state.pc = DEBUG_ROM_EXCEPTION;
     }
+    return;
   }
-  catch(trap_t& t)
-  {
-    state.pc = take_trap(t, pc);
-  }
-
-  update_timer(&state, instret);
-}
 
-void processor_t::push_privilege_stack()
-{
-  reg_t s = state.mstatus;
-  s = set_field(s, MSTATUS_PRV2, get_field(state.mstatus, MSTATUS_PRV1));
-  s = set_field(s, MSTATUS_IE2, get_field(state.mstatus, MSTATUS_IE1));
-  s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV));
-  s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE));
-  s = set_field(s, MSTATUS_PRV, PRV_M);
-  s = set_field(s, MSTATUS_MPRV, 0);
-  s = set_field(s, MSTATUS_IE, 0);
-  set_csr(CSR_MSTATUS, s);
-}
-
-void processor_t::pop_privilege_stack()
-{
-  reg_t s = state.mstatus;
-  s = set_field(s, MSTATUS_PRV, get_field(state.mstatus, MSTATUS_PRV1));
-  s = set_field(s, MSTATUS_IE, get_field(state.mstatus, MSTATUS_IE1));
-  s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV2));
-  s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE2));
-  s = set_field(s, MSTATUS_PRV2, PRV_U);
-  s = set_field(s, MSTATUS_IE2, 1);
-  set_csr(CSR_MSTATUS, s);
-}
+  if (t.cause() == CAUSE_BREAKPOINT && (
+              (state.prv == PRV_M && state.dcsr.ebreakm) ||
+              (state.prv == PRV_H && state.dcsr.ebreakh) ||
+              (state.prv == PRV_S && state.dcsr.ebreaks) ||
+              (state.prv == PRV_U && state.dcsr.ebreaku))) {
+    enter_debug_mode(DCSR_CAUSE_SWBP);
+    return;
+  }
 
-reg_t processor_t::take_trap(trap_t& t, reg_t epc)
-{
-  if (debug)
-    fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
-            id, t.name(), epc);
+  // by default, trap to M-mode, unless delegated to S-mode
+  reg_t bit = t.cause();
+  reg_t deleg = state.medeleg;
+  if (bit & ((reg_t)1 << (max_xlen-1)))
+    deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
+  if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
+    // handle the trap in S-mode
+    state.pc = state.stvec;
+    state.scause = t.cause();
+    state.sepc = epc;
+    if (t.has_badaddr())
+      state.sbadaddr = t.get_badaddr();
+
+    reg_t s = state.mstatus;
+    s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
+    s = set_field(s, MSTATUS_SPP, state.prv);
+    s = set_field(s, MSTATUS_SIE, 0);
+    set_csr(CSR_MSTATUS, s);
+    set_privilege(PRV_S);
+  } else {
+    state.pc = state.mtvec;
+    state.mepc = epc;
+    state.mcause = t.cause();
+    if (t.has_badaddr())
+      state.mbadaddr = t.get_badaddr();
+
+    reg_t s = state.mstatus;
+    s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
+    s = set_field(s, MSTATUS_MPP, state.prv);
+    s = set_field(s, MSTATUS_MIE, 0);
+    set_csr(CSR_MSTATUS, s);
+    set_privilege(PRV_M);
+  }
 
-  reg_t tvec = DEFAULT_MTVEC + 0x40 * get_field(state.mstatus, MSTATUS_PRV);
-  push_privilege_stack();
   yield_load_reservation();
-  state.mcause = t.cause();
-  state.mepc = epc;
-  t.side_effects(&state); // might set badvaddr etc.
-  return tvec;
-}
-
-void processor_t::deliver_ipi()
-{
-  state.mip |= MIP_MSIP;
 }
 
 void processor_t::disasm(insn_t insn)
@@ -334,11 +275,6 @@ void processor_t::disasm(insn_t insn)
           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 }
 
-static bool validate_priv(reg_t priv)
-{
-  return priv == PRV_U || priv == PRV_S || priv == PRV_M;
-}
-
 static bool validate_vm(int max_xlen, reg_t vm)
 {
   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
@@ -348,8 +284,17 @@ static bool validate_vm(int max_xlen, reg_t vm)
   return vm == VM_MBARE;
 }
 
+int processor_t::paddr_bits()
+{
+  assert(xlen == max_xlen);
+  return max_xlen == 64 ? 50 : 34;
+}
+
 void processor_t::set_csr(int which, reg_t val)
 {
+  val = zext_xlen(val);
+  reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
+  reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
   switch (which)
   {
     case CSR_FFLAGS:
@@ -365,47 +310,17 @@ void processor_t::set_csr(int which, reg_t val)
       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
       break;
-    case CSR_MTIME:
-    case CSR_STIMEW:
-      state.mtime = val;
-      break;
-    case CSR_MTIMEH:
-    case CSR_STIMEHW:
-      if (xlen == 32)
-        state.mtime = (uint32_t)val | (state.mtime >> 32 << 32);
-      else
-        state.mtime = val;
-      break;
-    case CSR_CYCLEW:
-    case CSR_TIMEW:
-    case CSR_INSTRETW:
-      val -= state.mtime;
-      if (xlen == 32)
-        state.sutime_delta = (uint32_t)val | (state.sutime_delta >> 32 << 32);
-      else
-        state.sutime_delta = val;
-      break;
-    case CSR_CYCLEHW:
-    case CSR_TIMEHW:
-    case CSR_INSTRETHW:
-      val -= state.mtime;
-      state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta;
-      break;
     case CSR_MSTATUS: {
-      if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_PRV1 | MSTATUS_MPRV))
+      if ((val ^ state.mstatus) &
+          (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR))
         mmu->flush_tlb();
 
-      reg_t mask = MSTATUS_IE | MSTATUS_IE1 | MSTATUS_IE2 | MSTATUS_MPRV
-                   | MSTATUS_FS | (ext ? MSTATUS_XS : 0);
+      reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
+                 | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
+                 | MSTATUS_MPP | MSTATUS_MXR | (ext ? MSTATUS_XS : 0);
 
       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
         mask |= MSTATUS_VM;
-      if (validate_priv(get_field(val, MSTATUS_PRV)))
-        mask |= MSTATUS_PRV;
-      if (validate_priv(get_field(val, MSTATUS_PRV1)))
-        mask |= MSTATUS_PRV1;
-      if (validate_priv(get_field(val, MSTATUS_PRV2)))
-        mask |= MSTATUS_PRV2;
 
       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 
@@ -422,58 +337,160 @@ void processor_t::set_csr(int which, reg_t val)
       break;
     }
     case CSR_MIP: {
-      reg_t mask = MIP_SSIP | MIP_MSIP;
+      reg_t mask = MIP_SSIP | MIP_STIP;
       state.mip = (state.mip & ~mask) | (val & mask);
       break;
     }
-    case CSR_MIE: {
-      reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP;
-      state.mie = (state.mie & ~mask) | (val & mask);
+    case CSR_MIE:
+      state.mie = (state.mie & ~all_ints) | (val & all_ints);
+      break;
+    case CSR_MIDELEG:
+      state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
+      break;
+    case CSR_MEDELEG: {
+      reg_t mask = 0;
+#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
+#include "encoding.h"
+#undef DECLARE_CAUSE
+      state.medeleg = (state.medeleg & ~mask) | (val & mask);
       break;
     }
+    case CSR_MINSTRET:
+    case CSR_MCYCLE:
+      if (xlen == 32)
+        state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
+      else
+        state.minstret = val;
+      break;
+    case CSR_MINSTRETH:
+    case CSR_MCYCLEH:
+      state.minstret = (val << 32) | (state.minstret << 32 >> 32);
+      break;
+    case CSR_MUCOUNTEREN:
+      state.mucounteren = val;
+      break;
+    case CSR_MSCOUNTEREN:
+      state.mscounteren = val;
+      break;
     case CSR_SSTATUS: {
-      reg_t ms = state.mstatus;
-      ms = set_field(ms, MSTATUS_IE, get_field(val, SSTATUS_IE));
-      ms = set_field(ms, MSTATUS_IE1, get_field(val, SSTATUS_PIE));
-      ms = set_field(ms, MSTATUS_PRV1, get_field(val, SSTATUS_PS));
-      ms = set_field(ms, MSTATUS_FS, get_field(val, SSTATUS_FS));
-      ms = set_field(ms, MSTATUS_XS, get_field(val, SSTATUS_XS));
-      ms = set_field(ms, MSTATUS_MPRV, get_field(val, SSTATUS_MPRV));
-      return set_csr(CSR_MSTATUS, ms);
+      reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
+                 | SSTATUS_XS | SSTATUS_PUM;
+      return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
     }
     case CSR_SIP: {
-      reg_t mask = MIP_SSIP;
-      state.mip = (state.mip & ~mask) | (val & mask);
-      break;
+      reg_t mask = MIP_SSIP & state.mideleg;
+      return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
     }
-    case CSR_SIE: {
-      reg_t mask = MIP_SSIP | MIP_STIP;
-      state.mie = (state.mie & ~mask) | (val & mask);
+    case CSR_SIE:
+      return set_csr(CSR_MIE,
+                     (state.mie & ~state.mideleg) | (val & state.mideleg));
+    case CSR_SPTBR: {
+      // upper bits of sptbr are the ASID; we only support ASID = 0
+      state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
       break;
     }
     case CSR_SEPC: state.sepc = val; break;
-    case CSR_STVEC: state.stvec = val & ~3; break;
-    case CSR_STIMECMP:
-      state.mip &= ~MIP_STIP;
-      state.stimecmp = val;
-      break;
-    case CSR_SPTBR: state.sptbr = zext_xlen(val & -PGSIZE); break;
+    case CSR_STVEC: state.stvec = val >> 2 << 2; break;
     case CSR_SSCRATCH: state.sscratch = val; break;
+    case CSR_SCAUSE: state.scause = val; break;
+    case CSR_SBADADDR: state.sbadaddr = val; break;
     case CSR_MEPC: state.mepc = val; break;
+    case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
     case CSR_MSCRATCH: state.mscratch = val; break;
     case CSR_MCAUSE: state.mcause = val; break;
     case CSR_MBADADDR: state.mbadaddr = val; break;
-    case CSR_SEND_IPI: sim->send_ipi(val); break;
-    case CSR_MTOHOST:
-      if (state.tohost == 0)
-        state.tohost = val;
+    case CSR_MISA: {
+      if (!(val & (1L << ('F' - 'A'))))
+        val &= ~(1L << ('D' - 'A'));
+
+      // allow MAFDC bits in MISA to be modified
+      reg_t mask = 0;
+      mask |= 1L << ('M' - 'A');
+      mask |= 1L << ('A' - 'A');
+      mask |= 1L << ('F' - 'A');
+      mask |= 1L << ('D' - 'A');
+      mask |= 1L << ('C' - 'A');
+      mask &= max_isa;
+
+      isa = (val & mask) | (isa & ~mask);
+      break;
+    }
+    case CSR_TSELECT:
+      if (val < state.num_triggers) {
+        state.tselect = val;
+      }
+      break;
+    case CSR_TDATA1:
+      {
+        mcontrol_t *mc = &state.mcontrol[state.tselect];
+        if (mc->dmode && !state.dcsr.cause) {
+          break;
+        }
+        mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
+        mc->select = get_field(val, MCONTROL_SELECT);
+        mc->timing = get_field(val, MCONTROL_TIMING);
+        mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
+        mc->chain = get_field(val, MCONTROL_CHAIN);
+        mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
+        mc->m = get_field(val, MCONTROL_M);
+        mc->h = get_field(val, MCONTROL_H);
+        mc->s = get_field(val, MCONTROL_S);
+        mc->u = get_field(val, MCONTROL_U);
+        mc->execute = get_field(val, MCONTROL_EXECUTE);
+        mc->store = get_field(val, MCONTROL_STORE);
+        mc->load = get_field(val, MCONTROL_LOAD);
+        // Assume we're here because of csrw.
+        if (mc->execute)
+          mc->timing = 0;
+        trigger_updated();
+      }
+      break;
+    case CSR_TDATA2:
+      if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
+        break;
+      }
+      if (state.tselect < state.num_triggers) {
+        state.tdata2[state.tselect] = val;
+      }
+      break;
+    case CSR_DCSR:
+      state.dcsr.prv = get_field(val, DCSR_PRV);
+      state.dcsr.step = get_field(val, DCSR_STEP);
+      // TODO: ndreset and fullreset
+      state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
+      state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
+      state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
+      state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
+      state.dcsr.halt = get_field(val, DCSR_HALT);
+      break;
+    case CSR_DPC:
+      state.dpc = val;
+      break;
+    case CSR_DSCRATCH:
+      state.dscratch = val;
       break;
-    case CSR_MFROMHOST: state.fromhost = val; break;
   }
 }
 
 reg_t processor_t::get_csr(int which)
 {
+  reg_t ctr_en = state.prv == PRV_U ? state.mucounteren :
+                 state.prv == PRV_S ? state.mscounteren : -1U;
+  bool ctr_ok = (ctr_en >> (which & 31)) & 1;
+
+  if (ctr_ok) {
+    if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
+      return 0;
+    if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
+      return 0;
+  }
+  if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
+    return 0;
+  if (xlen == 32 && which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
+    return 0;
+  if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
+    return 0;
+
   switch (which)
   {
     case CSR_FFLAGS:
@@ -491,54 +508,40 @@ reg_t processor_t::get_csr(int which)
       if (!supports_extension('F'))
         break;
       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
-    case CSR_MTIME:
-    case CSR_STIMEW:
-      return state.mtime;
-    case CSR_MTIMEH:
-    case CSR_STIMEHW:
-      return state.mtime >> 32;
-    case CSR_CYCLE:
-    case CSR_TIME:
     case CSR_INSTRET:
-    case CSR_STIME:
-    case CSR_CYCLEW:
-    case CSR_TIMEW:
-    case CSR_INSTRETW:
-      return state.mtime + state.sutime_delta;
-    case CSR_CYCLEH:
-    case CSR_TIMEH:
-    case CSR_INSTRETH:
-    case CSR_STIMEH:
-    case CSR_CYCLEHW:
-    case CSR_TIMEHW:
-    case CSR_INSTRETHW:
-      if (xlen == 64)
-        break;
-      return (state.mtime + state.sutime_delta) >> 32;
+    case CSR_CYCLE:
+      if (ctr_ok)
+        return state.minstret;
+      break;
+    case CSR_MINSTRET:
+    case CSR_MCYCLE:
+      return state.minstret;
+    case CSR_MINSTRETH:
+    case CSR_MCYCLEH:
+      if (xlen == 32)
+        return state.minstret >> 32;
+      break;
+    case CSR_MUCOUNTEREN: return state.mucounteren;
+    case CSR_MSCOUNTEREN: return state.mscounteren;
     case CSR_SSTATUS: {
-      reg_t ss = 0;
-      ss = set_field(ss, SSTATUS_IE, get_field(state.mstatus, MSTATUS_IE));
-      ss = set_field(ss, SSTATUS_PIE, get_field(state.mstatus, MSTATUS_IE1));
-      ss = set_field(ss, SSTATUS_PS, get_field(state.mstatus, MSTATUS_PRV1));
-      ss = set_field(ss, SSTATUS_FS, get_field(state.mstatus, MSTATUS_FS));
-      ss = set_field(ss, SSTATUS_XS, get_field(state.mstatus, MSTATUS_XS));
-      ss = set_field(ss, SSTATUS_MPRV, get_field(state.mstatus, MSTATUS_MPRV));
-      if (get_field(state.mstatus, MSTATUS64_SD))
-        ss = set_field(ss, (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD), 1);
-      return ss;
+      reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
+                 | SSTATUS_XS | SSTATUS_PUM;
+      reg_t sstatus = state.mstatus & mask;
+      if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
+          (sstatus & SSTATUS_XS) == SSTATUS_XS)
+        sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
+      return sstatus;
     }
-    case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
-    case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
+    case CSR_SIP: return state.mip & state.mideleg;
+    case CSR_SIE: return state.mie & state.mideleg;
     case CSR_SEPC: return state.sepc;
     case CSR_SBADADDR: return state.sbadaddr;
     case CSR_STVEC: return state.stvec;
-    case CSR_STIMECMP: return state.stimecmp;
     case CSR_SCAUSE:
       if (max_xlen > xlen)
         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
       return state.scause;
     case CSR_SPTBR: return state.sptbr;
-    case CSR_SASID: return 0;
     case CSR_SSCRATCH: return state.sscratch;
     case CSR_MSTATUS: return state.mstatus;
     case CSR_MIP: return state.mip;
@@ -547,35 +550,70 @@ reg_t processor_t::get_csr(int which)
     case CSR_MSCRATCH: return state.mscratch;
     case CSR_MCAUSE: return state.mcause;
     case CSR_MBADADDR: return state.mbadaddr;
-    case CSR_MCPUID: return cpuid;
-    case CSR_MIMPID: return IMPL_ROCKET;
+    case CSR_MISA: return isa;
+    case CSR_MARCHID: return 0;
+    case CSR_MIMPID: return 0;
+    case CSR_MVENDORID: return 0;
     case CSR_MHARTID: return id;
-    case CSR_MTVEC: return DEFAULT_MTVEC;
-    case CSR_MTDELEG: return 0;
-    case CSR_MTOHOST:
-      sim->get_htif()->tick(); // not necessary, but faster
-      return state.tohost;
-    case CSR_MFROMHOST:
-      sim->get_htif()->tick(); // not necessary, but faster
-      return state.fromhost;
-    case CSR_SEND_IPI: return 0;
-    case CSR_UARCH0:
-    case CSR_UARCH1:
-    case CSR_UARCH2:
-    case CSR_UARCH3:
-    case CSR_UARCH4:
-    case CSR_UARCH5:
-    case CSR_UARCH6:
-    case CSR_UARCH7:
-    case CSR_UARCH8:
-    case CSR_UARCH9:
-    case CSR_UARCH10:
-    case CSR_UARCH11:
-    case CSR_UARCH12:
-    case CSR_UARCH13:
-    case CSR_UARCH14:
-    case CSR_UARCH15:
-      return 0;
+    case CSR_MTVEC: return state.mtvec;
+    case CSR_MEDELEG: return state.medeleg;
+    case CSR_MIDELEG: return state.mideleg;
+    case CSR_TSELECT: return state.tselect;
+    case CSR_TDATA1:
+      if (state.tselect < state.num_triggers) {
+        reg_t v = 0;
+        mcontrol_t *mc = &state.mcontrol[state.tselect];
+        v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
+        v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
+        v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
+        v = set_field(v, MCONTROL_SELECT, mc->select);
+        v = set_field(v, MCONTROL_TIMING, mc->timing);
+        v = set_field(v, MCONTROL_ACTION, mc->action);
+        v = set_field(v, MCONTROL_CHAIN, mc->chain);
+        v = set_field(v, MCONTROL_MATCH, mc->match);
+        v = set_field(v, MCONTROL_M, mc->m);
+        v = set_field(v, MCONTROL_H, mc->h);
+        v = set_field(v, MCONTROL_S, mc->s);
+        v = set_field(v, MCONTROL_U, mc->u);
+        v = set_field(v, MCONTROL_EXECUTE, mc->execute);
+        v = set_field(v, MCONTROL_STORE, mc->store);
+        v = set_field(v, MCONTROL_LOAD, mc->load);
+        return v;
+      } else {
+        return 0;
+      }
+      break;
+    case CSR_TDATA2:
+      if (state.tselect < state.num_triggers) {
+        return state.tdata2[state.tselect];
+      } else {
+        return 0;
+      }
+      break;
+    case CSR_TDATA3: return 0;
+    case CSR_DCSR:
+      {
+        uint32_t v = 0;
+        v = set_field(v, DCSR_XDEBUGVER, 1);
+        v = set_field(v, DCSR_NDRESET, 0);
+        v = set_field(v, DCSR_FULLRESET, 0);
+        v = set_field(v, DCSR_PRV, state.dcsr.prv);
+        v = set_field(v, DCSR_STEP, state.dcsr.step);
+        v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
+        v = set_field(v, DCSR_STOPCYCLE, 0);
+        v = set_field(v, DCSR_STOPTIME, 0);
+        v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
+        v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
+        v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
+        v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
+        v = set_field(v, DCSR_HALT, state.dcsr.halt);
+        v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
+        return v;
+      }
+    case CSR_DPC:
+      return state.dpc;
+    case CSR_DSCRATCH:
+      return state.dscratch;
   }
   throw trap_illegal_instruction();
 }
@@ -587,55 +625,51 @@ reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 
 insn_func_t processor_t::decode_insn(insn_t insn)
 {
-  size_t mask = opcode_map.size()-1;
-  insn_desc_t* desc = opcode_map[insn.bits() & mask]; 
+  // look up opcode in hash table
+  size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
+  insn_desc_t desc = opcode_cache[idx];
+
+  if (unlikely(insn.bits() != desc.match)) {
+    // fall back to linear search
+    insn_desc_t* p = &instructions[0];
+    while ((insn.bits() & p->mask) != p->match)
+      p++;
+    desc = *p;
+
+    if (p->mask != 0 && p > &instructions[0]) {
+      if (p->match != (p-1)->match && p->match != (p+1)->match) {
+        // move to front of opcode list to reduce miss penalty
+        while (--p >= &instructions[0])
+          *(p+1) = *p;
+        instructions[0] = desc;
+      }
+    }
 
-  while ((insn.bits() & desc->mask) != desc->match)
-    desc++;
+    opcode_cache[idx] = desc;
+    opcode_cache[idx].match = insn.bits();
+  }
 
-  return xlen == 64 ? desc->rv64 : desc->rv32;
+  return xlen == 64 ? desc.rv64 : desc.rv32;
 }
 
 void processor_t::register_insn(insn_desc_t desc)
 {
-  assert(desc.mask & 1);
   instructions.push_back(desc);
 }
 
 void processor_t::build_opcode_map()
 {
-  size_t buckets = -1;
-  for (auto& inst : instructions)
-    while ((inst.mask & buckets) != buckets)
-      buckets /= 2;
-  buckets++;
-
   struct cmp {
-    decltype(insn_desc_t::match) mask;
-    cmp(decltype(mask) mask) : mask(mask) {}
     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
-      if ((lhs.match & mask) != (rhs.match & mask))
-        return (lhs.match & mask) < (rhs.match & mask);
-      return lhs.match < rhs.match;
+      if (lhs.match == rhs.match)
+        return lhs.mask > rhs.mask;
+      return lhs.match > rhs.match;
     }
   };
-  std::sort(instructions.begin(), instructions.end(), cmp(buckets-1));
-
-  opcode_map.resize(buckets);
-  opcode_store.resize(instructions.size() + 1);
-
-  size_t j = 0;
-  for (size_t b = 0, i = 0; b < buckets; b++)
-  {
-    opcode_map[b] = &opcode_store[j];
-    while (i < instructions.size() && b == (instructions[i].match & (buckets-1)))
-      opcode_store[j++] = instructions[i++];
-  }
+  std::sort(instructions.begin(), instructions.end(), cmp());
 
-  assert(j == opcode_store.size()-1);
-  opcode_store[j].match = opcode_store[j].mask = 0;
-  opcode_store[j].rv32 = &illegal_instruction;
-  opcode_store[j].rv64 = &illegal_instruction;
+  for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
+    opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 }
 
 void processor_t::register_extension(extension_t* x)
@@ -650,3 +684,59 @@ void processor_t::register_extension(extension_t* x)
   ext = x;
   x->set_processor(this);
 }
+
+void processor_t::register_base_instructions()
+{
+  #define DECLARE_INSN(name, match, mask) \
+    insn_bits_t name##_match = (match), name##_mask = (mask);
+  #include "encoding.h"
+  #undef DECLARE_INSN
+
+  #define DEFINE_INSN(name) \
+    REGISTER_INSN(this, name, name##_match, name##_mask)
+  #include "insn_list.h"
+  #undef DEFINE_INSN
+
+  register_insn({0, 0, &illegal_instruction, &illegal_instruction});
+  build_opcode_map();
+}
+
+bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
+{
+  return false;
+}
+
+bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
+{
+  switch (addr)
+  {
+    case 0:
+      state.mip &= ~MIP_MSIP;
+      if (bytes[0] & 1)
+        state.mip |= MIP_MSIP;
+      return true;
+
+    default:
+      return false;
+  }
+}
+
+void processor_t::trigger_updated()
+{
+  mmu->flush_tlb();
+  mmu->check_triggers_fetch = false;
+  mmu->check_triggers_load = false;
+  mmu->check_triggers_store = false;
+
+  for (unsigned i = 0; i < state.num_triggers; i++) {
+    if (state.mcontrol[i].execute) {
+      mmu->check_triggers_fetch = true;
+    }
+    if (state.mcontrol[i].load) {
+      mmu->check_triggers_load = true;
+    }
+    if (state.mcontrol[i].store) {
+      mmu->check_triggers_store = true;
+    }
+  }
+}