X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.cc;h=067378700982f44f12d2ddd662be5baabfa8af55;hb=c0c61f09d8eb21a41b5472a85abdcac62ad665d6;hp=eea2ce2078a24409ebf5475a4511216154a7fb04;hpb=2641a9b24f176ca3edf83c471276fdc8f1d0ea86;p=riscv-isa-sim.git

diff --git a/riscv/processor.cc b/riscv/processor.cc
index eea2ce2..0673787 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -1,269 +1,614 @@
+// See LICENSE for license details.
+
 #include "processor.h"
-#include <bfd.h>
-#include <dis-asm.h>
-#include <cmath>
-#include <cstdlib>
-#include <iostream>
+#include "extension.h"
 #include "common.h"
 #include "config.h"
 #include "sim.h"
-#include "icsim.h"
+#include "htif.h"
+#include "disasm.h"
+#include <cinttypes>
+#include <cmath>
+#include <cstdlib>
+#include <iostream>
+#include <assert.h>
+#include <limits.h>
+#include <stdexcept>
+#include <algorithm>
 
-processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
-  : sim(_sim), mmu(_mem,_memsz)
+#undef STATE
+#define STATE state
+
+processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
+  : sim(sim), ext(NULL), disassembler(new disassembler_t),
+    id(id), run(false), debug(false)
 {
-  // a few assumptions about endianness, including freg_t union
-  static_assert(BYTE_ORDER == LITTLE_ENDIAN);
-  static_assert(sizeof(freg_t) == 8);
-  static_assert(sizeof(reg_t) == 8);
+  parse_isa_string(isa);
 
-  static_assert(sizeof(insn_t) == 4);
-  static_assert(sizeof(uint128_t) == 16 && sizeof(int128_t) == 16);
+  mmu = new mmu_t(sim->mem, sim->memsz);
+  mmu->set_processor(this);
 
-  icsim = NULL;
-  dcsim = NULL;
-  itlbsim = NULL;
-  dtlbsim = NULL;
+  reset(true);
 
-  reset();
+  register_base_instructions();
 }
 
 processor_t::~processor_t()
 {
-  if(icsim)
-    icsim->print_stats();
-  delete icsim;
-
-  if(itlbsim)
-    itlbsim->print_stats();
-  delete itlbsim;
+#ifdef RISCV_ENABLE_HISTOGRAM
+  if (histogram_enabled)
+  {
+    fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
+    for (auto it : pc_histogram)
+      fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
+  }
+#endif
 
-  if(dcsim)
-    dcsim->print_stats();
-  delete dcsim;
+  delete mmu;
+  delete disassembler;
+}
 
-  if(dtlbsim)
-    dtlbsim->print_stats();
-  delete dtlbsim;
+static void bad_isa_string(const char* isa)
+{
+  fprintf(stderr, "error: bad --isa option %s\n", isa);
+  abort();
 }
 
-void processor_t::init(uint32_t _id, icsim_t* default_icache,
-                       icsim_t* default_dcache)
+void processor_t::parse_isa_string(const char* str)
 {
-  id = _id;
+  std::string lowercase, tmp;
+  for (const char *r = str; *r; r++)
+    lowercase += std::tolower(*r);
+
+  const char* p = lowercase.c_str();
+  const char* all_subsets = "imafdc";
+
+  max_xlen = 64;
+  cpuid = reg_t(2) << 62;
+
+  if (strncmp(p, "rv32", 4) == 0)
+    max_xlen = 32, cpuid = 0, p += 4;
+  else if (strncmp(p, "rv64", 4) == 0)
+    p += 4;
+  else if (strncmp(p, "rv", 2) == 0)
+    p += 2;
+
+  if (!*p) {
+    p = all_subsets;
+  } else if (*p == 'g') { // treat "G" as "IMAFD"
+    tmp = std::string("imafd") + (p+1);
+    p = &tmp[0];
+  } else if (*p != 'i') {
+    bad_isa_string(str);
+  }
 
-  for (int i=0; i<MAX_UTS; i++)
-  {
-    uts[i] = new processor_t(sim, mmu.mem, mmu.memsz);
-    uts[i]->id = id;
-    uts[i]->set_sr(uts[i]->sr | SR_EF);
-    uts[i]->set_sr(uts[i]->sr | SR_EV);
-    uts[i]->utidx = i;
+  isa = "rv" + std::to_string(max_xlen) + p;
+  cpuid |= 1L << ('s' - 'a'); // advertise support for supervisor mode
+
+  while (*p) {
+    cpuid |= 1L << (*p - 'a');
+
+    if (auto next = strchr(all_subsets, *p)) {
+      all_subsets = next + 1;
+      p++;
+    } else if (*p == 'x') {
+      const char* ext = p+1, *end = ext;
+      while (islower(*end))
+        end++;
+      register_extension(find_extension(std::string(ext, end - ext).c_str())());
+      p = end;
+    } else {
+      bad_isa_string(str);
+    }
   }
 
-  #ifdef RISCV_ENABLE_ICSIM
-  icsim = new icsim_t(*default_icache);
-  mmu.set_icsim(icsim);
-  itlbsim = new icsim_t(1, 8, 4096, "ITLB");
-  mmu.set_itlbsim(itlbsim);
-  #endif
-  #ifdef RISCV_ENABLE_ICSIM
-  dcsim = new icsim_t(*default_dcache);
-  mmu.set_dcsim(dcsim);
-  dtlbsim = new icsim_t(1, 8, 4096, "DTLB");
-  mmu.set_dtlbsim(dtlbsim);
-  #endif
+  if (supports_extension('D') && !supports_extension('F'))
+    bad_isa_string(str);
 }
 
-void processor_t::reset()
+void state_t::reset()
 {
-  run = false;
-
-  memset(XPR,0,sizeof(XPR));
-  memset(FPR,0,sizeof(FPR));
-
-  pc = 0;
-  evec = 0;
-  epc = 0;
-  badvaddr = 0;
-  cause = 0;
-  pcr_k0 = 0;
-  pcr_k1 = 0;
-  tohost = 0;
-  fromhost = 0;
-  count = 0;
-  compare = 0;
-  cycle = 0;
-  set_sr(SR_S | SR_SX);  // SX ignored if 64b mode not supported
-  set_fsr(0);
-
-  // vector stuff
-  vecbanks = 0xff;
-  vecbanks_count = 8;
-  utidx = -1;
-  vlmax = 32;
-  vl = 0;
-  nxfpr_bank = 256;
-  nxpr_use = 32;
-  nfpr_use = 32;
-  for (int i=0; i<MAX_UTS; i++)
-    uts[i] = NULL;
+  memset(this, 0, sizeof(*this));
+  prv = PRV_M;
+  pc = DEFAULT_RSTVEC;
+  load_reservation = -1;
 }
 
-void processor_t::set_sr(uint32_t val)
+void processor_t::set_debug(bool value)
 {
-  sr = val & ~SR_ZERO;
-#ifndef RISCV_ENABLE_64BIT
-  sr &= ~(SR_SX | SR_UX);
-#endif
-#ifndef RISCV_ENABLE_FPU
-  sr &= ~SR_EF;
-#endif
-#ifndef RISCV_ENABLE_RVC
-  sr &= ~SR_EC;
-#endif
-#ifndef RISCV_ENABLE_VEC
-  sr &= ~SR_EV;
+  debug = value;
+  if (ext)
+    ext->set_debug(value);
+}
+
+void processor_t::set_histogram(bool value)
+{
+  histogram_enabled = value;
+#ifndef RISCV_ENABLE_HISTOGRAM
+  if (value) {
+    fprintf(stderr, "PC Histogram support has not been properly enabled;");
+    fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
+  }
 #endif
+}
 
-  mmu.set_vm_enabled(sr & SR_VM);
-  mmu.set_supervisor(sr & SR_S);
-  mmu.flush_tlb();
+void processor_t::reset(bool value)
+{
+  if (run == !value)
+    return;
+  run = !value;
 
-  xprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32;
+  state.reset();
+  set_csr(CSR_MSTATUS, state.mstatus);
+
+  if (ext)
+    ext->reset(); // reset the extension
 }
 
-void processor_t::set_fsr(uint32_t val)
+void processor_t::raise_interrupt(reg_t which)
 {
-  fsr = val & ~FSR_ZERO;
+  throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 }
 
-void processor_t::vcfg()
+static int ctz(reg_t val)
 {
-  if (nxpr_use + nfpr_use < 2)
-    vlmax = nxfpr_bank * vecbanks_count;
-  else
-    vlmax = (nxfpr_bank / (nxpr_use + nfpr_use - 1)) * vecbanks_count;
+  int res = 0;
+  if (val)
+    while ((val & 1) == 0)
+      val >>= 1, res++;
+  return res;
+}
+
+void processor_t::take_interrupt()
+{
+  check_timer();
+
+  reg_t interrupts = state.mip & state.mie;
+
+  reg_t m_interrupts = interrupts & ~state.mideleg;
+  reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
+  if ((state.prv < PRV_M || (state.prv == PRV_M && mie)) && m_interrupts)
+    raise_interrupt(ctz(m_interrupts));
 
-  vlmax = std::min(vlmax, MAX_UTS);
+  reg_t s_interrupts = interrupts & state.mideleg;
+  reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
+  if ((state.prv < PRV_S || (state.prv == PRV_S && sie)) && s_interrupts)
+    raise_interrupt(ctz(s_interrupts));
 }
 
-void processor_t::setvl(int vlapp)
+void processor_t::check_timer()
 {
-  vl = std::min(vlmax, vlapp);
+  if (sim->rtc >= state.mtimecmp)
+    state.mip |= MIP_MTIP;
 }
 
-void processor_t::take_interrupt()
+static bool validate_priv(reg_t priv)
 {
-  uint32_t interrupts = (cause & CAUSE_IP) >> CAUSE_IP_SHIFT;
-  interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
+  return priv == PRV_U || priv == PRV_S || priv == PRV_M;
+}
 
-  if(interrupts && (sr & SR_ET))
-    throw trap_interrupt;
+void processor_t::set_privilege(reg_t prv)
+{
+  assert(validate_priv(prv));
+  mmu->flush_tlb();
+  state.prv = prv;
 }
 
-void processor_t::step(size_t n, bool noisy)
+void processor_t::take_trap(trap_t& t, reg_t epc)
 {
-  if(!run)
-    return;
+  if (debug)
+    fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
+            id, t.name(), epc);
+
+  // by default, trap to M-mode, unless delegated to S-mode
+  reg_t bit = t.cause();
+  reg_t deleg = state.medeleg;
+  if (bit & ((reg_t)1 << (max_xlen-1)))
+    deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
+  if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
+    // handle the trap in S-mode
+    state.pc = state.stvec;
+    state.scause = t.cause();
+    state.sepc = epc;
+    if (t.has_badaddr())
+      state.sbadaddr = t.get_badaddr();
+
+    reg_t s = state.mstatus;
+    s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
+    s = set_field(s, MSTATUS_SPP, state.prv);
+    s = set_field(s, MSTATUS_SIE, 0);
+    set_csr(CSR_MSTATUS, s);
+    set_privilege(PRV_S);
+  } else {
+    state.pc = DEFAULT_MTVEC;
+    state.mcause = t.cause();
+    state.mepc = epc;
+    if (t.has_badaddr())
+      state.mbadaddr = t.get_badaddr();
+
+    reg_t s = state.mstatus;
+    s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
+    s = set_field(s, MSTATUS_MPP, state.prv);
+    s = set_field(s, MSTATUS_MIE, 0);
+    set_csr(CSR_MSTATUS, s);
+    set_privilege(PRV_M);
+  }
 
-  size_t i = 0;
-  while(1) try
-  {
-    take_interrupt();
-
-    #include "dispatch.h"
-
-    #define execute_insn(noisy) \
-      do { insn_t insn = mmu.load_insn(pc, sr & SR_EC); \
-      if(noisy) disasm(insn,pc); \
-      pc = dispatch_table[dispatch_index(insn)](this, insn, pc); \
-      XPR[0] = 0; } while(0)
-
-    if(noisy) for( ; i < n; i++)
-      execute_insn(true);
-    else 
-    {
-      for( ; n > 3 && i < n-3; i+=4)
-      {
-        execute_insn(false);
-        execute_insn(false);
-        execute_insn(false);
-        execute_insn(false);
-      }
-      for( ; i < n; i++)
-        execute_insn(false);
-    }
+  yield_load_reservation();
+}
 
-    break;
-  }
-  catch(trap_t t)
-  {
-    i++;
-    take_trap(t,noisy);
-  }
-  catch(vt_command_t cmd)
+void processor_t::disasm(insn_t insn)
+{
+  uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
+  fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
+          id, state.pc, bits, disassembler->disassemble(insn).c_str());
+}
+
+static bool validate_vm(int max_xlen, reg_t vm)
+{
+  if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
+    return true;
+  if (max_xlen == 32 && vm == VM_SV32)
+    return true;
+  return vm == VM_MBARE;
+}
+
+void processor_t::set_csr(int which, reg_t val)
+{
+  val = zext_xlen(val);
+  reg_t all_ints = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP | (1UL << IRQ_HOST);
+  reg_t s_ints = MIP_SSIP | MIP_STIP;
+  switch (which)
   {
-    i++;
-    if (cmd == vt_command_stop)
+    case CSR_FFLAGS:
+      dirty_fp_state;
+      state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
+      break;
+    case CSR_FRM:
+      dirty_fp_state;
+      state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
+      break;
+    case CSR_FCSR:
+      dirty_fp_state;
+      state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
+      state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
+      break;
+    case CSR_MTIME:
+    case CSR_STIMEW:
+      // this implementation ignores writes to MTIME
+      break;
+    case CSR_MTIMEH:
+    case CSR_STIMEHW:
+      // this implementation ignores writes to MTIME
+      break;
+    case CSR_TIMEW:
+      val -= sim->rtc;
+      if (xlen == 32)
+        state.sutime_delta = val | (state.sutime_delta >> 32 << 32);
+      else
+        state.sutime_delta = val;
+      break;
+    case CSR_TIMEHW:
+      val = ((val << 32) - sim->rtc) >> 32;
+      state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta;
+      break;
+    case CSR_CYCLEW:
+    case CSR_INSTRETW:
+      val -= state.minstret;
+      if (xlen == 32)
+        state.suinstret_delta = val | (state.suinstret_delta >> 32 << 32);
+      else
+        state.suinstret_delta = val;
+      break;
+    case CSR_CYCLEHW:
+    case CSR_INSTRETHW:
+      val = ((val << 32) - state.minstret) >> 32;
+      state.suinstret_delta = (val << 32) | (uint32_t)state.suinstret_delta;
+      break;
+    case CSR_MSTATUS: {
+      if ((val ^ state.mstatus) &
+          (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
+        mmu->flush_tlb();
+
+      reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
+                 | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
+                 | (ext ? MSTATUS_XS : 0);
+
+      if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
+        mask |= MSTATUS_VM;
+      if (validate_priv(get_field(val, MSTATUS_MPP)))
+        mask |= MSTATUS_MPP;
+
+      state.mstatus = (state.mstatus & ~mask) | (val & mask);
+
+      bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
+      dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
+      if (max_xlen == 32)
+        state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
+      else
+        state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
+
+      // spike supports the notion of xlen < max_xlen, but current priv spec
+      // doesn't provide a mechanism to run RV32 software on an RV64 machine
+      xlen = max_xlen;
+      break;
+    }
+    case CSR_MIP: {
+      reg_t mask = all_ints &~ MIP_MTIP;
+      state.mip = (state.mip & ~mask) | (val & mask);
+      break;
+    }
+    case CSR_MIPI:
+      state.mip = set_field(state.mip, MIP_MSIP, val & 1);
+      break;
+    case CSR_MIE:
+      state.mie = (state.mie & ~all_ints) | (val & all_ints);
+      break;
+    case CSR_MIDELEG:
+      state.mideleg = (state.mideleg & ~s_ints) | (val & s_ints);
+      break;
+    case CSR_MEDELEG: {
+      reg_t mask = 0;
+#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
+#include "encoding.h"
+#undef DECLARE_CAUSE
+      state.medeleg = (state.medeleg & ~mask) | (val & mask);
+      break;
+    }
+    case CSR_SSTATUS: {
+      reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
+                 | SSTATUS_XS | SSTATUS_PUM;
+      set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
+      break;
+    }
+    case CSR_SIP: {
+      reg_t mask = s_ints &~ MIP_STIP;
+      state.mip = (state.mip & ~mask) | (val & mask);
+      break;
+    }
+    case CSR_SIE: {
+      reg_t mask = s_ints;
+      state.mie = (state.mie & ~mask) | (val & mask);
+      break;
+    }
+    case CSR_SEPC: state.sepc = val; break;
+    case CSR_STVEC: state.stvec = val >> 2 << 2; break;
+    case CSR_SPTBR: state.sptbr = val; break;
+    case CSR_SSCRATCH: state.sscratch = val; break;
+    case CSR_SCAUSE: state.scause = val; break;
+    case CSR_SBADADDR: state.sbadaddr = val; break;
+    case CSR_MEPC: state.mepc = val; break;
+    case CSR_MSCRATCH: state.mscratch = val; break;
+    case CSR_MCAUSE: state.mcause = val; break;
+    case CSR_MBADADDR: state.mbadaddr = val; break;
+    case CSR_MTIMECMP:
+      state.mip &= ~MIP_MTIP;
+      state.mtimecmp = val;
+      break;
+    case CSR_MTOHOST:
+      if (state.tohost == 0)
+        state.tohost = val;
+      break;
+    case CSR_MFROMHOST:
+      state.mip = (state.mip & ~(1 << IRQ_HOST)) | (val ? (1 << IRQ_HOST) : 0);
+      state.fromhost = val;
       break;
   }
-  catch(halt_t t)
+}
+
+reg_t processor_t::get_csr(int which)
+{
+  switch (which)
   {
-    reset();
-    return;
+    case CSR_FFLAGS:
+      require_fp;
+      if (!supports_extension('F'))
+        break;
+      return state.fflags;
+    case CSR_FRM:
+      require_fp;
+      if (!supports_extension('F'))
+        break;
+      return state.frm;
+    case CSR_FCSR:
+      require_fp;
+      if (!supports_extension('F'))
+        break;
+      return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
+    case CSR_MTIME:
+    case CSR_STIME:
+    case CSR_STIMEW:
+      return sim->rtc;
+    case CSR_MTIMEH:
+    case CSR_STIMEH:
+    case CSR_STIMEHW:
+      return sim->rtc >> 32;
+    case CSR_TIME:
+    case CSR_TIMEW:
+      return sim->rtc + state.sutime_delta;
+    case CSR_CYCLE:
+    case CSR_CYCLEW:
+    case CSR_INSTRET:
+    case CSR_INSTRETW:
+      return state.minstret + state.suinstret_delta;
+    case CSR_TIMEH:
+    case CSR_TIMEHW:
+      if (xlen == 64)
+        break;
+      return (sim->rtc + state.sutime_delta) >> 32;
+    case CSR_CYCLEH:
+    case CSR_INSTRETH:
+    case CSR_CYCLEHW:
+    case CSR_INSTRETHW:
+      if (xlen == 64)
+        break;
+      return (state.minstret + state.suinstret_delta) >> 32;
+    case CSR_SSTATUS: {
+      reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
+                 | SSTATUS_XS | SSTATUS_PUM;
+      reg_t sstatus = state.mstatus & mask;
+      if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
+          (sstatus & SSTATUS_XS) == SSTATUS_XS)
+        sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
+      return sstatus;
+    }
+    case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
+    case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
+    case CSR_SEPC: return state.sepc;
+    case CSR_SBADADDR: return state.sbadaddr;
+    case CSR_STVEC: return state.stvec;
+    case CSR_SCAUSE:
+      if (max_xlen > xlen)
+        return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
+      return state.scause;
+    case CSR_SPTBR: return state.sptbr;
+    case CSR_SASID: return 0;
+    case CSR_SSCRATCH: return state.sscratch;
+    case CSR_MSTATUS: return state.mstatus;
+    case CSR_MIP: return state.mip;
+    case CSR_MIPI: return 0;
+    case CSR_MIE: return state.mie;
+    case CSR_MEPC: return state.mepc;
+    case CSR_MSCRATCH: return state.mscratch;
+    case CSR_MCAUSE: return state.mcause;
+    case CSR_MBADADDR: return state.mbadaddr;
+    case CSR_MTIMECMP: return state.mtimecmp;
+    case CSR_MCPUID: return cpuid;
+    case CSR_MIMPID: return IMPL_ROCKET;
+    case CSR_MHARTID: return id;
+    case CSR_MTVEC: return DEFAULT_MTVEC;
+    case CSR_MEDELEG: return state.medeleg;
+    case CSR_MIDELEG: return state.mideleg;
+    case CSR_MTOHOST:
+      sim->get_htif()->tick(); // not necessary, but faster
+      return state.tohost;
+    case CSR_MFROMHOST:
+      sim->get_htif()->tick(); // not necessary, but faster
+      return state.fromhost;
+    case CSR_MIOBASE: return sim->memsz;
+    case CSR_UARCH0:
+    case CSR_UARCH1:
+    case CSR_UARCH2:
+    case CSR_UARCH3:
+    case CSR_UARCH4:
+    case CSR_UARCH5:
+    case CSR_UARCH6:
+    case CSR_UARCH7:
+    case CSR_UARCH8:
+    case CSR_UARCH9:
+    case CSR_UARCH10:
+    case CSR_UARCH11:
+    case CSR_UARCH12:
+    case CSR_UARCH13:
+    case CSR_UARCH14:
+    case CSR_UARCH15:
+      return 0;
+  }
+  throw trap_illegal_instruction();
+}
+
+reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
+{
+  throw trap_illegal_instruction();
+}
+
+insn_func_t processor_t::decode_insn(insn_t insn)
+{
+  // look up opcode in hash table
+  size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
+  insn_desc_t desc = opcode_cache[idx];
+
+  if (unlikely(insn.bits() != desc.match)) {
+    // fall back to linear search
+    insn_desc_t* p = &instructions[0];
+    while ((insn.bits() & p->mask) != p->match)
+      p++;
+    desc = *p;
+
+    if (p->mask != 0 && p > &instructions[0]) {
+      if (p->match != (p-1)->match && p->match != (p+1)->match) {
+        // move to front of opcode list to reduce miss penalty
+        while (--p >= &instructions[0])
+          *(p+1) = *p;
+        instructions[0] = desc;
+      }
+    }
+
+    opcode_cache[idx] = desc;
+    opcode_cache[idx].match = insn.bits();
   }
 
-  cycle += i;
+  return xlen == 64 ? desc.rv64 : desc.rv32;
+}
 
-  typeof(count) old_count = count;
-  typeof(count) max_count = -1;
-  count += i;
-  if(old_count < compare && (count >= compare || old_count > max_count-i))
-    cause |= 1 << (TIMER_IRQ+CAUSE_IP_SHIFT);
+void processor_t::register_insn(insn_desc_t desc)
+{
+  instructions.push_back(desc);
 }
 
-void processor_t::take_trap(trap_t t, bool noisy)
+void processor_t::build_opcode_map()
 {
-  demand(t < NUM_TRAPS, "internal error: bad trap number %d", int(t));
-  demand(sr & SR_ET, "error mode on core %d!\ntrap %s, pc 0x%016llx",
-         id, trap_name(t), (unsigned long long)pc);
-  if(noisy)
-    printf("core %3d: trap %s, pc 0x%016llx\n",
-           id, trap_name(t), (unsigned long long)pc);
-
-  set_sr((((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
-  cause = (cause & ~CAUSE_EXCCODE) | (t << CAUSE_EXCCODE_SHIFT);
-  epc = pc;
-  pc = evec;
-  badvaddr = mmu.get_badvaddr();
+  struct cmp {
+    bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
+      if (lhs.match == rhs.match)
+        return lhs.mask > rhs.mask;
+      return lhs.match > rhs.match;
+    }
+  };
+  std::sort(instructions.begin(), instructions.end(), cmp());
+
+  for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
+    opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 }
 
-void processor_t::deliver_ipi()
+void processor_t::register_extension(extension_t* x)
 {
-  cause |= 1 << (IPI_IRQ+CAUSE_IP_SHIFT);
-  run = true;
+  for (auto insn : x->get_instructions())
+    register_insn(insn);
+  build_opcode_map();
+  for (auto disasm_insn : x->get_disasms())
+    disassembler->add_insn(disasm_insn);
+  if (ext != NULL)
+    throw std::logic_error("only one extension may be registered");
+  ext = x;
+  x->set_processor(this);
 }
 
-void processor_t::disasm(insn_t insn, reg_t pc)
+void processor_t::register_base_instructions()
 {
-  printf("core %3d: 0x%016llx (0x%08x) ",id,(unsigned long long)pc,insn.bits);
-
-  #ifdef RISCV_HAVE_LIBOPCODES
-  disassemble_info info;
-  INIT_DISASSEMBLE_INFO(info, stdout, fprintf);
-  info.flavour = bfd_target_unknown_flavour;
-  info.arch = bfd_arch_mips;
-  info.mach = 101; // XXX bfd_mach_mips_riscv requires modified bfd.h
-  info.endian = BFD_ENDIAN_LITTLE;
-  info.buffer = (bfd_byte*)&insn;
-  info.buffer_length = sizeof(insn);
-  info.buffer_vma = pc;
-
-  int ret = print_insn_little_mips(pc, &info);
-  demand(ret == insn_length(insn.bits), "disasm bug!");
-  #else
-  printf("unknown");
-  #endif
-  printf("\n");
+  #define DECLARE_INSN(name, match, mask) \
+    insn_bits_t name##_match = (match), name##_mask = (mask);
+  #include "encoding.h"
+  #undef DECLARE_INSN
+
+  #define DEFINE_INSN(name) \
+    REGISTER_INSN(this, name, name##_match, name##_mask)
+  #include "insn_list.h"
+  #undef DEFINE_INSN
+
+  register_insn({0, 0, &illegal_instruction, &illegal_instruction});
+  build_opcode_map();
+}
+
+bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
+{
+  try {
+    auto res = get_csr(addr / (max_xlen / 8));
+    memcpy(bytes, &res, len);
+    return true;
+  } catch (trap_illegal_instruction& t) {
+    return false;
+  }
+}
+
+bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
+{
+  try {
+    reg_t value = 0;
+    memcpy(&value, bytes, len);
+    set_csr(addr / (max_xlen / 8), value);
+    return true;
+  } catch (trap_illegal_instruction& t) {
+    return false;
+  }
 }