X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.cc;h=a9be33454ababab3144115eded12ecabb3dd97a0;hb=d6dae451821656d7676fec3ec515691d4c66e065;hp=4c4e3dd110ee5f352895e7ee34667e5b9c3765c4;hpb=dd233bc49946aa059b6ea9494b870d20076ce1b8;p=riscv-isa-sim.git diff --git a/riscv/processor.cc b/riscv/processor.cc index 4c4e3dd..a9be334 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -6,7 +6,6 @@ #include "config.h" #include "sim.h" #include "mmu.h" -#include "htif.h" #include "disasm.h" #include "gdbserver.h" #include @@ -21,17 +20,17 @@ #undef STATE #define STATE state -processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id) - : debug(false), sim(sim), ext(NULL), disassembler(new disassembler_t), - id(id), run(false) +processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id, + bool halt_on_reset) + : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset) { parse_isa_string(isa); + register_base_instructions(); mmu = new mmu_t(sim, this); + disassembler = new disassembler_t(max_xlen); - reset(true); - - register_base_instructions(); + reset(); } processor_t::~processor_t() @@ -85,6 +84,7 @@ void processor_t::parse_isa_string(const char* str) isa_string = "rv" + std::to_string(max_xlen) + p; isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode + isa |= 1L << ('u' - 'a'); // advertise support for user mode while (*p) { isa |= 1L << (*p - 'a'); @@ -118,6 +118,12 @@ void state_t::reset() pc = DEFAULT_RSTVEC; mtvec = DEFAULT_MTVEC; load_reservation = -1; + tselect = 0; + for (unsigned int i = 0; i < num_triggers; i++) { + mcontrol[i].type = 2; + mcontrol[i].action = ACTION_NONE; + tdata1[i] = 0; + } } void processor_t::set_debug(bool value) @@ -138,13 +144,11 @@ void processor_t::set_histogram(bool value) #endif } -void processor_t::reset(bool value) +void processor_t::reset() { - if (run == !value) - return; - run = !value; - state.reset(); + state.dcsr.halt = halt_on_reset; + halt_on_reset = false; set_csr(CSR_MSTATUS, state.mstatus); if (ext) @@ -156,6 +160,7 @@ void processor_t::raise_interrupt(reg_t which) throw trap_t(((reg_t)1 << (max_xlen-1)) | which); } +// Count number of contiguous 0 bits starting from the LSB. static int ctz(reg_t val) { int res = 0; @@ -181,27 +186,24 @@ void processor_t::take_interrupt() raise_interrupt(ctz(enabled_interrupts)); } -static bool validate_priv(reg_t priv) -{ - return priv == PRV_U || priv == PRV_S || priv == PRV_M; -} - void processor_t::set_privilege(reg_t prv) { - assert(validate_priv(prv)); + assert(prv <= PRV_M); + if (prv == PRV_H) + prv = PRV_U; mmu->flush_tlb(); state.prv = prv; } void processor_t::enter_debug_mode(uint8_t cause) { - fprintf(stderr, "enter_debug_mode(%d), mstatus=0x%lx, prv=0x%lx\n", cause, state.mstatus, state.prv); state.dcsr.cause = cause; state.dcsr.prv = state.prv; set_privilege(PRV_M); state.dpc = state.pc; state.pc = DEBUG_ROM_START; - debug = true; // TODO + //debug = true; // TODO + update_slow_path(); } void processor_t::take_trap(trap_t& t, reg_t epc) @@ -214,12 +216,20 @@ void processor_t::take_trap(trap_t& t, reg_t epc) t.get_badaddr()); } - if (t.cause() == CAUSE_BREAKPOINT && - sim->gdbserver && sim->gdbserver->connected()) { + if (t.cause() == CAUSE_BREAKPOINT && ( + (state.prv == PRV_M && state.dcsr.ebreakm) || + (state.prv == PRV_H && state.dcsr.ebreakh) || + (state.prv == PRV_S && state.dcsr.ebreaks) || + (state.prv == PRV_U && state.dcsr.ebreaku))) { enter_debug_mode(DCSR_CAUSE_SWBP); return; } + if (state.dcsr.cause) { + state.pc = DEBUG_ROM_EXCEPTION; + return; + } + // by default, trap to M-mode, unless delegated to S-mode reg_t bit = t.cause(); reg_t deleg = state.medeleg; @@ -240,13 +250,9 @@ void processor_t::take_trap(trap_t& t, reg_t epc) set_csr(CSR_MSTATUS, s); set_privilege(PRV_S); } else { - if (state.dcsr.cause) { - state.pc = DEBUG_ROM_EXCEPTION; - } else { - state.pc = state.mtvec; - } - state.mcause = t.cause(); + state.pc = state.mtvec; state.mepc = epc; + state.mcause = t.cause(); if (t.has_badaddr()) state.mbadaddr = t.get_badaddr(); @@ -277,9 +283,14 @@ static bool validate_vm(int max_xlen, reg_t vm) return vm == VM_MBARE; } +int processor_t::paddr_bits() +{ + assert(xlen == max_xlen); + return max_xlen == 64 ? 50 : 34; +} + void processor_t::set_csr(int which, reg_t val) { - fprintf(stderr, "set_csr(0x%x, 0x%lx)\n", which, val); val = zext_xlen(val); reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP); reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP; @@ -300,17 +311,15 @@ void processor_t::set_csr(int which, reg_t val) break; case CSR_MSTATUS: { if ((val ^ state.mstatus) & - (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM)) + (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR)) mmu->flush_tlb(); reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM - | (ext ? MSTATUS_XS : 0); + | MSTATUS_MPP | MSTATUS_MXR | (ext ? MSTATUS_XS : 0); if (validate_vm(max_xlen, get_field(val, MSTATUS_VM))) mask |= MSTATUS_VM; - if (validate_priv(get_field(val, MSTATUS_MPP))) - mask |= MSTATUS_MPP; state.mstatus = (state.mstatus & ~mask) | (val & mask); @@ -362,9 +371,13 @@ void processor_t::set_csr(int which, reg_t val) case CSR_SIE: return set_csr(CSR_MIE, (state.mie & ~state.mideleg) | (val & state.mideleg)); + case CSR_SPTBR: { + // upper bits of sptbr are the ASID; we only support ASID = 0 + state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1); + break; + } case CSR_SEPC: state.sepc = val; break; case CSR_STVEC: state.stvec = val >> 2 << 2; break; - case CSR_SPTBR: state.sptbr = val; break; case CSR_SSCRATCH: state.sscratch = val; break; case CSR_SCAUSE: state.scause = val; break; case CSR_SBADADDR: state.sbadaddr = val; break; @@ -373,21 +386,44 @@ void processor_t::set_csr(int which, reg_t val) case CSR_MSCRATCH: state.mscratch = val; break; case CSR_MCAUSE: state.mcause = val; break; case CSR_MBADADDR: state.mbadaddr = val; break; - case DCSR_ADDRESS: - // TODO: Use get_field style - state.dcsr.prv = (val & DCSR_PRV_MASK) >> DCSR_PRV_OFFSET; - state.dcsr.step = (val & DCSR_STEP_MASK) >> DCSR_STEP_OFFSET; + case CSR_TSELECT: state.tselect = val; break; + case CSR_TDATA0: + if (state.tselect < state.num_triggers) { + mcontrol_t *mc = &state.mcontrol[state.tselect]; + mc->select = get_field(val, MCONTROL_SELECT); + mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION); + mc->chain = get_field(val, MCONTROL_CHAIN); + mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH); + mc->m = get_field(val, MCONTROL_M); + mc->h = get_field(val, MCONTROL_H); + mc->s = get_field(val, MCONTROL_S); + mc->u = get_field(val, MCONTROL_U); + mc->execute = get_field(val, MCONTROL_EXECUTE); + mc->store = get_field(val, MCONTROL_STORE); + mc->load = get_field(val, MCONTROL_LOAD); + // Assume we're here because of csrw. + trigger_updated(); + } + break; + case CSR_TDATA1: + if (state.tselect < state.num_triggers) { + state.tdata1[state.tselect] = val; + } + break; + case CSR_DCSR: + state.dcsr.prv = get_field(val, DCSR_PRV); + state.dcsr.step = get_field(val, DCSR_STEP); // TODO: ndreset and fullreset - state.dcsr.ebreakm = (val & DCSR_EBREAKM_MASK) >> DCSR_EBREAKM_OFFSET; - state.dcsr.ebreakh = (val & DCSR_EBREAKH_MASK) >> DCSR_EBREAKH_OFFSET; - state.dcsr.ebreaks = (val & DCSR_EBREAKS_MASK) >> DCSR_EBREAKS_OFFSET; - state.dcsr.ebreaku = (val & DCSR_EBREAKU_MASK) >> DCSR_EBREAKU_OFFSET; - state.dcsr.halt = (val & DCSR_HALT_MASK) >> DCSR_HALT_OFFSET; + state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM); + state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH); + state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS); + state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU); + state.dcsr.halt = get_field(val, DCSR_HALT); break; - case DPC_ADDRESS: + case CSR_DPC: state.dpc = val; break; - case DSCRATCH_ADDRESS: + case CSR_DSCRATCH: state.dscratch = val; break; } @@ -461,7 +497,6 @@ reg_t processor_t::get_csr(int which) return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1)); return state.scause; case CSR_SPTBR: return state.sptbr; - case CSR_SASID: return 0; case CSR_SSCRATCH: return state.sscratch; case CSR_MSTATUS: return state.mstatus; case CSR_MIP: return state.mip; @@ -478,29 +513,59 @@ reg_t processor_t::get_csr(int which) case CSR_MTVEC: return state.mtvec; case CSR_MEDELEG: return state.medeleg; case CSR_MIDELEG: return state.mideleg; - case DCSR_ADDRESS: + case CSR_TSELECT: return state.tselect; + case CSR_TDATA0: + if (state.tselect < state.num_triggers) { + reg_t v = 0; + mcontrol_t *mc = &state.mcontrol[state.tselect]; + v = set_field(v, 0xfL << (xlen-4), mc->type); + v = set_field(v, 0x3fL << (xlen-10), mc->maskmax); + v = set_field(v, MCONTROL_SELECT, mc->select); + v = set_field(v, MCONTROL_ACTION, mc->action); + v = set_field(v, MCONTROL_CHAIN, mc->chain); + v = set_field(v, MCONTROL_MATCH, mc->match); + v = set_field(v, MCONTROL_M, mc->m); + v = set_field(v, MCONTROL_H, mc->h); + v = set_field(v, MCONTROL_S, mc->s); + v = set_field(v, MCONTROL_U, mc->u); + v = set_field(v, MCONTROL_EXECUTE, mc->execute); + v = set_field(v, MCONTROL_STORE, mc->store); + v = set_field(v, MCONTROL_LOAD, mc->load); + return v; + } else { + return 0; + } + break; + case CSR_TDATA1: + if (state.tselect < state.num_triggers) { + return state.tdata1[state.tselect]; + } else { + return 0; + } + break; + case CSR_DCSR: { - uint32_t value = - (1 << DCSR_XDEBUGVER_OFFSET) | - (0 << DCSR_HWBPCOUNT_OFFSET) | - (0 << DCSR_NDRESET_OFFSET) | - (0 << DCSR_FULLRESET_OFFSET) | - (state.dcsr.prv << DCSR_PRV_OFFSET) | - (state.dcsr.step << DCSR_STEP_OFFSET) | - (sim->debug_module.get_interrupt(id) << DCSR_DEBUGINT_OFFSET) | - (0 << DCSR_STOPCYCLE_OFFSET) | - (0 << DCSR_STOPTIME_OFFSET) | - (state.dcsr.ebreakm << DCSR_EBREAKM_OFFSET) | - (state.dcsr.ebreakh << DCSR_EBREAKH_OFFSET) | - (state.dcsr.ebreaks << DCSR_EBREAKS_OFFSET) | - (state.dcsr.ebreaku << DCSR_EBREAKU_OFFSET) | - (state.dcsr.halt << DCSR_HALT_OFFSET) | - (state.dcsr.cause << DCSR_CAUSE_OFFSET); - return value; + uint32_t v = 0; + v = set_field(v, DCSR_XDEBUGVER, 1); + v = set_field(v, DCSR_HWBPCOUNT, 0); + v = set_field(v, DCSR_NDRESET, 0); + v = set_field(v, DCSR_FULLRESET, 0); + v = set_field(v, DCSR_PRV, state.dcsr.prv); + v = set_field(v, DCSR_STEP, state.dcsr.step); + v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id)); + v = set_field(v, DCSR_STOPCYCLE, 0); + v = set_field(v, DCSR_STOPTIME, 0); + v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm); + v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh); + v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks); + v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku); + v = set_field(v, DCSR_HALT, state.dcsr.halt); + v = set_field(v, DCSR_CAUSE, state.dcsr.cause); + return v; } - case DPC_ADDRESS: + case CSR_DPC: return state.dpc; - case DSCRATCH_ADDRESS: + case CSR_DSCRATCH: return state.dscratch; } throw trap_illegal_instruction(); @@ -557,7 +622,7 @@ void processor_t::build_opcode_map() std::sort(instructions.begin(), instructions.end(), cmp()); for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++) - opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction}; + opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction}; } void processor_t::register_extension(extension_t* x) @@ -608,3 +673,25 @@ bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes) return false; } } + +void processor_t::trigger_updated() +{ + mmu->flush_tlb(); + mmu->check_triggers_fetch = false; + mmu->check_triggers_load = false; + mmu->check_triggers_store = false; + + for (unsigned i = 0; i < state.num_triggers; i++) { + if (state.mcontrol[i].action == ACTION_NONE) + continue; + if (state.mcontrol[i].execute) { + mmu->check_triggers_fetch = true; + } + if (state.mcontrol[i].load) { + mmu->check_triggers_load = true; + } + if (state.mcontrol[i].store) { + mmu->check_triggers_store = true; + } + } +}