X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.cc;h=b2c2d344ec0e3db50120db13e09153d2e706d108;hb=8fda4e00ea7326d6f2a2867c7482559bf5b0b401;hp=d44f870574d1ccced46717248c78347f51974a87;hpb=6db070768733f415fc9bf54582708364ca0e294b;p=riscv-isa-sim.git diff --git a/riscv/processor.cc b/riscv/processor.cc index d44f870..b2c2d34 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -7,7 +7,6 @@ #include "sim.h" #include "mmu.h" #include "disasm.h" -#include "gdbserver.h" #include #include #include @@ -22,7 +21,8 @@ processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id, bool halt_on_reset) - : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset) + : debug(false), halt_request(false), sim(sim), ext(NULL), id(id), + halt_on_reset(halt_on_reset) { parse_isa_string(isa); register_base_instructions(); @@ -118,7 +118,6 @@ void state_t::reset() memset(this, 0, sizeof(*this)); prv = PRV_M; pc = DEFAULT_RSTVEC; - mtvec = DEFAULT_MTVEC; load_reservation = -1; tselect = 0; for (unsigned int i = 0; i < num_triggers; i++) @@ -190,11 +189,12 @@ void processor_t::set_privilege(reg_t prv) void processor_t::enter_debug_mode(uint8_t cause) { + fprintf(stderr, "Entering debug mode because of cause %d", cause); state.dcsr.cause = cause; state.dcsr.prv = state.prv; set_privilege(PRV_M); state.dpc = state.pc; - state.pc = DEBUG_ROM_START; + state.pc = debug_rom_entry(); } void processor_t::take_trap(trap_t& t, reg_t epc) @@ -207,6 +207,15 @@ void processor_t::take_trap(trap_t& t, reg_t epc) t.get_badaddr()); } + if (state.dcsr.cause) { + if (t.cause() == CAUSE_BREAKPOINT) { + state.pc = debug_rom_entry(); + } else { + state.pc = DEBUG_ROM_TVEC; + } + return; + } + if (t.cause() == CAUSE_BREAKPOINT && ( (state.prv == PRV_M && state.dcsr.ebreakm) || (state.prv == PRV_H && state.dcsr.ebreakh) || @@ -216,15 +225,11 @@ void processor_t::take_trap(trap_t& t, reg_t epc) return; } - if (state.dcsr.cause) { - state.pc = DEBUG_ROM_EXCEPTION; - return; - } - // by default, trap to M-mode, unless delegated to S-mode reg_t bit = t.cause(); reg_t deleg = state.medeleg; - if (bit & ((reg_t)1 << (max_xlen-1))) + bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0; + if (interrupt) deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1)); if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) { // handle the trap in S-mode @@ -235,20 +240,21 @@ void processor_t::take_trap(trap_t& t, reg_t epc) state.sbadaddr = t.get_badaddr(); reg_t s = state.mstatus; - s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv)); + s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); s = set_field(s, MSTATUS_SPP, state.prv); s = set_field(s, MSTATUS_SIE, 0); set_csr(CSR_MSTATUS, s); set_privilege(PRV_S); } else { - state.pc = state.mtvec; + reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0; + state.pc = (state.mtvec & ~(reg_t)1) + vector; state.mepc = epc; state.mcause = t.cause(); if (t.has_badaddr()) state.mbadaddr = t.get_badaddr(); reg_t s = state.mstatus; - s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv)); + s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); s = set_field(s, MSTATUS_MPP, state.prv); s = set_field(s, MSTATUS_MIE, 0); set_csr(CSR_MSTATUS, s); @@ -260,9 +266,23 @@ void processor_t::take_trap(trap_t& t, reg_t epc) void processor_t::disasm(insn_t insn) { + static uint64_t last_pc = 1, last_bits; + static uint64_t executions = 1; + uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1); - fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n", - id, state.pc, bits, disassembler->disassemble(insn).c_str()); + if (last_pc != state.pc || last_bits != bits) { + if (executions != 1) { + fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions); + } + + fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n", + id, state.pc, bits, disassembler->disassemble(insn).c_str()); + last_pc = state.pc; + last_bits = bits; + executions = 1; + } else { + executions++; + } } int processor_t::paddr_bits() @@ -293,12 +313,13 @@ void processor_t::set_csr(int which, reg_t val) break; case CSR_MSTATUS: { if ((val ^ state.mstatus) & - (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR)) + (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR)) mmu->flush_tlb(); reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE - | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM - | MSTATUS_MPP | MSTATUS_MXR | (ext ? MSTATUS_XS : 0); + | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM + | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM + | MSTATUS_TSR | (ext ? MSTATUS_XS : 0); state.mstatus = (state.mstatus & ~mask) | (val & mask); @@ -352,7 +373,7 @@ void processor_t::set_csr(int which, reg_t val) break; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS - | SSTATUS_XS | SSTATUS_PUM; + | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR; return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask)); } case CSR_SIP: { @@ -367,7 +388,8 @@ void processor_t::set_csr(int which, reg_t val) if (max_xlen == 32) state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE); if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF || - get_field(val, SPTBR64_MODE) >= SPTBR_MODE_SV39)) + get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 || + get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48)) state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE); break; } @@ -377,7 +399,7 @@ void processor_t::set_csr(int which, reg_t val) case CSR_SCAUSE: state.scause = val; break; case CSR_SBADADDR: state.sbadaddr = val; break; case CSR_MEPC: state.mepc = val; break; - case CSR_MTVEC: state.mtvec = val >> 2 << 2; break; + case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break; case CSR_MSCRATCH: state.mscratch = val; break; case CSR_MCAUSE: state.mcause = val; break; case CSR_MBADADDR: state.mbadaddr = val; break; @@ -510,7 +532,7 @@ reg_t processor_t::get_csr(int which) case CSR_MCOUNTEREN: return state.mcounteren; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS - | SSTATUS_XS | SSTATUS_PUM; + | SSTATUS_XS | SSTATUS_SUM; reg_t sstatus = state.mstatus & mask; if ((sstatus & SSTATUS_FS) == SSTATUS_FS || (sstatus & SSTATUS_XS) == SSTATUS_XS) @@ -526,7 +548,10 @@ reg_t processor_t::get_csr(int which) if (max_xlen > xlen) return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1)); return state.scause; - case CSR_SPTBR: return state.sptbr; + case CSR_SPTBR: + if (get_field(state.mstatus, MSTATUS_TVM)) + require_privilege(PRV_M); + return state.sptbr; case CSR_SSCRATCH: return state.sscratch; case CSR_MSTATUS: return state.mstatus; case CSR_MIP: return state.mip; @@ -580,19 +605,15 @@ reg_t processor_t::get_csr(int which) { uint32_t v = 0; v = set_field(v, DCSR_XDEBUGVER, 1); - v = set_field(v, DCSR_NDRESET, 0); - v = set_field(v, DCSR_FULLRESET, 0); - v = set_field(v, DCSR_PRV, state.dcsr.prv); - v = set_field(v, DCSR_STEP, state.dcsr.step); - v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id)); - v = set_field(v, DCSR_STOPCYCLE, 0); - v = set_field(v, DCSR_STOPTIME, 0); v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm); v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh); v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks); v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku); - v = set_field(v, DCSR_HALT, state.dcsr.halt); + v = set_field(v, DCSR_STOPCYCLE, 0); + v = set_field(v, DCSR_STOPTIME, 0); v = set_field(v, DCSR_CAUSE, state.dcsr.cause); + v = set_field(v, DCSR_STEP, state.dcsr.step); + v = set_field(v, DCSR_PRV, state.dcsr.prv); return v; } case CSR_DPC: @@ -600,12 +621,12 @@ reg_t processor_t::get_csr(int which) case CSR_DSCRATCH: return state.dscratch; } - throw trap_illegal_instruction(); + throw trap_illegal_instruction(0); } reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc) { - throw trap_illegal_instruction(); + throw trap_illegal_instruction(0); } insn_func_t processor_t::decode_insn(insn_t insn)