X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.h;h=0224f10dc9aaf3afcfec907f395b064644aa9e2a;hb=9e012462f53113dc9ed00d7fbb89aeafeb9b89e9;hp=8a9ff47fdfdc6f02312f3328ae5710fc5dbcd7e3;hpb=6642f8c745b320bdb7bab2470c62defb1b1bb9e2;p=riscv-isa-sim.git

diff --git a/riscv/processor.h b/riscv/processor.h
index 8a9ff47..0224f10 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -167,7 +167,6 @@ public:
   void reset();
   void step(size_t n); // run for n cycles
   void set_csr(int which, reg_t val);
-  void raise_interrupt(reg_t which);
   reg_t get_csr(int which);
   mmu_t* get_mmu() { return mmu; }
   state_t* get_state() { return &state; }
@@ -297,8 +296,8 @@ private:
   static const size_t OPCODE_CACHE_SIZE = 8191;
   insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
 
-  void check_timer();
-  void take_interrupt(); // take a trap if any interrupts are pending
+  void take_pending_interrupt() { take_interrupt(state.mip & state.mie); }
+  void take_interrupt(reg_t mask); // take first enabled interrupt in mask
   void take_trap(trap_t& t, reg_t epc); // take an exception
   void disasm(insn_t insn); // disassemble and print an instruction
   int paddr_bits();