X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Friscv.ac;h=68bcdb55d17f175ca1c8a52a0d2df768375d475d;hb=1132fdf4f07dfbfba237af7b0cfac3cae543a79b;hp=636a8c401f21b9cafe6b8caa7fc473333a99aed5;hpb=504a07f261f25eb884c91b7008f85d669b025cb8;p=riscv-isa-sim.git

diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 636a8c4..68bcdb5 100644
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -1,37 +1,44 @@
-AC_ARG_ENABLE([fpu], AS_HELP_STRING([--disable-fpu], [Disable floating-point]))
-AS_IF([test "x$enable_fpu" != "xno"], [
-  AC_DEFINE([RISCV_ENABLE_FPU],,[Define if floating-point instructions are supported])
-])
+AC_LANG_CPLUSPLUS
 
-AC_ARG_ENABLE([64bit], AS_HELP_STRING([--disable-64bit], [Disable 64-bit mode]))
-AS_IF([test "x$enable_64bit" != "xno"], [
-  AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported])
-])
+AC_ARG_WITH(isa,
+	[AS_HELP_STRING([--with-isa=RV64IMAFDC],
+		[Sets the default RISC-V ISA])],
+  AC_DEFINE_UNQUOTED([DEFAULT_ISA], "$withval", [Default value for --isa switch]),
+  AC_DEFINE_UNQUOTED([DEFAULT_ISA], "RV64IMAFDC", [Default value for --isa switch]))
 
-AC_ARG_ENABLE([rvc], AS_HELP_STRING([--enable-rvc], [Enable instruction compression]))
-AS_IF([test "x$enable_rvc" = "xyes"], [
-  AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported])
+AC_SEARCH_LIBS([dlopen], [dl dld], [], [
+  AC_MSG_ERROR([unable to find the dlopen() function])
 ])
 
-AC_ARG_ENABLE([vec], AS_HELP_STRING([--disable-vec], [Disable vector processor]))
-AS_IF([test "x$enable_vec" != "xno"], [
-  AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported])
+AC_ARG_WITH([fesvr],
+  [AS_HELP_STRING([--with-fesvr],
+    [path to your fesvr installation if not in a standard location])],
+  [
+    LDFLAGS="-L$withval/lib $LDFLAGS"
+    CPPFLAGS="-I$withval/include $CPPFLAGS"
+  ]
+)
+
+AC_CHECK_LIB(fesvr, libfesvr_is_present, [], [AC_MSG_ERROR([libfesvr is required])], [-pthread])
+
+AC_CHECK_LIB(pthread, pthread_create, [], [AC_MSG_ERROR([libpthread is required])])
+
+AC_ARG_ENABLE([commitlog], AS_HELP_STRING([--enable-commitlog], [Enable commit log generation]))
+AS_IF([test "x$enable_commitlog" = "xyes"], [
+  AC_DEFINE([RISCV_ENABLE_COMMITLOG],,[Enable commit log generation])
 ])
 
-libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv-elf/lib/libopcodes.a
-AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"])
+AC_ARG_ENABLE([histogram], AS_HELP_STRING([--enable-histogram], [Enable PC histogram generation]))
+AS_IF([test "x$enable_histogram" = "xyes"], [
+  AC_DEFINE([RISCV_ENABLE_HISTOGRAM],,[Enable PC histogram generation])
+])
 
-libbfd="/opt/local/lib/libbfd.dylib"
-AC_SEARCH_LIBS([bfd_init],[bfd],[],[
-    AC_CHECK_FILES([$libbfd], [libopc="$libopc $libbfd" incopc="-I/opt/local/include"], [have_libopcodes="no"])
+AC_ARG_ENABLE([dirty], AS_HELP_STRING([--enable-dirty], [Enable hardware management of PTE accessed and dirty bits]))
+AS_IF([test "x$enable_dirty" = "xyes"], [
+  AC_DEFINE([RISCV_ENABLE_DIRTY],,[Enable hardware management of PTE accessed and dirty bits])
 ])
 
-AS_IF([test "$have_libopcodes" = "no"],[
-  AC_MSG_WARN([Could not find opcodes library])
-  AC_MSG_WARN([Build will not include disassembly support])
-],[
-  LIBS="$libopc $LIBS"
-  INCDIRS="$incopc"
-  AC_DEFINE([RISCV_HAVE_LIBOPCODES],,[Define if libopcodes exists])
+AC_ARG_ENABLE([misaligned], AS_HELP_STRING([--enable-misaligned], [Enable hardware support for misaligned loads and stores]))
+AS_IF([test "x$enable_misaligned" = "xyes"], [
+  AC_DEFINE([RISCV_ENABLE_MISALIGNED],,[Enable hardware support for misaligned loads and stores])
 ])
-AC_SUBST(INCDIRS)