X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Friscv.mk.in;fp=riscv%2Friscv.mk.in;h=233953f1ecd53286b729e6d671ef3db757c70c80;hb=545911797f15901dd5cc81014db01bb2b0f3f644;hp=f8abb1b592e1052662a29c6f4384a8f2beb9cd1c;hpb=d48f107dba6a96fb827cb47fdf290261feadeb35;p=riscv-isa-sim.git

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index f8abb1b..233953f 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -11,6 +11,7 @@ riscv_hdrs = \
 	decode.h \
 	devices.h \
 	disasm.h \
+	dts.h \
 	mmu.h \
 	processor.h \
 	sim.h \
@@ -33,6 +34,7 @@ riscv_precompiled_hdrs = \
 riscv_srcs = \
 	processor.cc \
 	execute.cc \
+	dts.cc \
 	sim.cc \
 	interactive.cc \
 	trap.cc \