X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Friscv.mk.in;h=40054cfbaa289793f4ca8051dc1edf0157be20e4;hb=bbbe41e6365732a489d76b3bac5f5fafd0208482;hp=552187ab19d077a833c416aaf41c8638140b480f;hpb=036c9086663024512dd0a8e5409b68187211c0bf;p=riscv-isa-sim.git

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 552187a..40054cf 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -23,8 +23,9 @@ riscv_hdrs = \
 	rocc.h \
 	insn_template.h \
 	mulhi.h \
-	gdbserver.h \
 	debug_module.h \
+	remote_bitbang.h \
+	jtag_dtm.h \
 
 riscv_precompiled_hdrs = \
 	insn_template.h \
@@ -44,9 +45,10 @@ riscv_srcs = \
 	regnames.cc \
 	devices.cc \
 	rom.cc \
-	rtc.cc \
-	gdbserver.cc \
+	clint.cc \
 	debug_module.cc \
+	remote_bitbang.cc \
+	jtag_dtm.cc \
 	$(riscv_gen_srcs) \
 
 riscv_test_srcs =
@@ -227,7 +229,7 @@ riscv_insn_list = \
 	sc_d \
 	sc_w \
 	sd \
-	sfence_vm \
+	sfence_vma \
 	sh \
 	sll \
 	slli \