X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Friscv.mk.in;h=695803b142ffb0b60b61d3673f379aee7eb8df47;hb=d1f2cf337e1a0be8eada2afadd745e1374b4a000;hp=2dfe4ed8ac8d88c07919cbf1f0c9d8b6a3007153;hpb=27e29e69cc586a7d97e2ccae2447faa79b66f7b8;p=riscv-isa-sim.git

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 2dfe4ed..695803b 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -7,9 +7,9 @@ riscv_subproject_deps = \
 riscv_install_prog_srcs = \
 
 riscv_hdrs = \
-	htif.h \
 	common.h \
 	decode.h \
+	devices.h \
 	disasm.h \
 	mmu.h \
 	processor.h \
@@ -18,16 +18,18 @@ riscv_hdrs = \
 	encoding.h \
 	cachesim.h \
 	memtracer.h \
+	tracer.h \
 	extension.h \
 	rocc.h \
 	insn_template.h \
 	mulhi.h \
+	debug_module.h \
+	remote_bitbang.h \
 
 riscv_precompiled_hdrs = \
 	insn_template.h \
 
 riscv_srcs = \
-	htif.cc \
 	processor.cc \
 	execute.cc \
 	sim.cc \
@@ -41,6 +43,10 @@ riscv_srcs = \
 	rocc.cc \
 	regnames.cc \
 	devices.cc \
+	rom.cc \
+	rtc.cc \
+	debug_module.cc \
+	remote_bitbang.cc \
 	$(riscv_gen_srcs) \
 
 riscv_test_srcs =
@@ -126,6 +132,7 @@ riscv_insn_list = \
 	divu \
 	divuw \
 	divw \
+	dret \
 	ebreak \
 	ecall \
 	fadd_d \