X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fsim.cc;h=bdf55e275bfec0e937c9804fe49e92610b982cc8;hb=693fc45eb8ccc3c9f84b898de3119a172e0776f5;hp=668d23a531e5a767209514865e878ab00a530f08;hpb=d9170d6002c684acdfca1ba124dba2235081b578;p=riscv-isa-sim.git diff --git a/riscv/sim.cc b/riscv/sim.cc index 668d23a..bdf55e2 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -1,232 +1,338 @@ +// See LICENSE for license details. + #include "sim.h" -#include "applink.h" -#include "common.h" -#include +#include "mmu.h" +#include "gdbserver.h" #include #include +#include +#include +#include +#include +#include +#include +#include +#include + +volatile bool ctrlc_pressed = false; +static void handle_signal(int sig) +{ + if (ctrlc_pressed) + exit(-1); + ctrlc_pressed = true; + signal(sig, &handle_signal); +} -sim_t::sim_t(int _nprocs, size_t _memsz, appserver_link_t* _applink) - : applink(_applink), - memsz(_memsz), - mem((char*)mmap64(NULL, memsz, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0)), - procs(std::vector(_nprocs,processor_t(this,mem,memsz))) +sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted, + const std::vector& args) + : htif_t(args), procs(std::max(nprocs, size_t(1))), + current_step(0), current_proc(0), debug(false), gdbserver(NULL) { - demand(mem != MAP_FAILED, "couldn't allocate target machine's memory"); + signal(SIGINT, &handle_signal); + // allocate target machine's memory, shrinking it as necessary + // until the allocation succeeds + size_t memsz0 = (size_t)mem_mb << 20; + size_t quantum = 1L << 20; + if (memsz0 == 0) + memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20; + + memsz = memsz0; + while ((mem = (char*)calloc(1, memsz)) == NULL) + memsz = (size_t)(memsz*0.9)/quantum*quantum; - for(int i = 0; i < (int)procs.size(); i++) - procs[i].init(i); + if (memsz != memsz0) + fprintf(stderr, "warning: only got %zu bytes of target mem (wanted %zu)\n", + memsz, memsz0); - applink->init(this); + bus.add_device(DEBUG_START, &debug_module); + + debug_mmu = new mmu_t(this, NULL); + + for (size_t i = 0; i < procs.size(); i++) { + procs[i] = new processor_t(isa, this, i, halted); + } + + rtc.reset(new rtc_t(procs)); + make_dtb(); } sim_t::~sim_t() { + for (size_t i = 0; i < procs.size(); i++) + delete procs[i]; + delete debug_mmu; + free(mem); } -void sim_t::set_tohost(reg_t val) +void sim_thread_main(void* arg) { - fromhost = 0; - tohost = val; + ((sim_t*)arg)->main(); } -reg_t sim_t::get_fromhost() +void sim_t::main() { - while(fromhost == 0) - applink->wait_for_packet(); - return fromhost; + if (!debug && log) + set_procs_debug(true); + + while (!done()) + { + if (debug || ctrlc_pressed) + interactive(); + else + step(INTERLEAVE); + if (gdbserver) { + gdbserver->handle(); + } + } } -void sim_t::run(bool debug) +int sim_t::run() { - applink->wait_for_start(); + host = context_t::current(); + target.init(sim_thread_main, this); + return htif_t::run(); +} - while(1) +void sim_t::step(size_t n) +{ + for (size_t i = 0, steps = 0; i < n; i += steps) { - if(!debug) - step_all(100,100,false); - else + steps = std::min(n - i, INTERLEAVE - current_step); + procs[current_proc]->step(steps); + + current_step += steps; + if (current_step == INTERLEAVE) { - putchar(':'); - char s[128]; - std::cin.getline(s,sizeof(s)-1); - - char* p = strtok(s," "); - if(!p) - { - interactive_run_noisy(std::vector(1,"1")); - continue; + current_step = 0; + procs[current_proc]->yield_load_reservation(); + if (++current_proc == procs.size()) { + current_proc = 0; + rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK); } - std::string cmd = p; - - std::vector args; - while((p = strtok(NULL," "))) - args.push_back(p); - - - typedef void (sim_t::*interactive_func)(const std::vector&); - std::map funcs; - funcs["r"] = &sim_t::interactive_run_noisy; - funcs["rs"] = &sim_t::interactive_run_silent; - funcs["rp"] = &sim_t::interactive_run_proc_noisy; - funcs["rps"] = &sim_t::interactive_run_proc_silent; - funcs["reg"] = &sim_t::interactive_reg; - funcs["mem"] = &sim_t::interactive_mem; - funcs["until"] = &sim_t::interactive_until; - funcs["q"] = &sim_t::interactive_quit; - - try - { - if(funcs.count(cmd)) - (this->*funcs[cmd])(args); - } - catch(trap_t t) {} + host->switch_to(); } } } -void sim_t::step_all(size_t n, size_t interleave, bool noisy) +void sim_t::set_debug(bool value) { - for(size_t j = 0; j < n; j+=interleave) - for(int i = 0; i < (int)procs.size(); i++) - procs[i].step(interleave,noisy); + debug = value; } -void sim_t::interactive_run_noisy(const std::vector& args) +void sim_t::set_log(bool value) { - interactive_run(args,true); + log = value; } -void sim_t::interactive_run_silent(const std::vector& args) +void sim_t::set_histogram(bool value) { - interactive_run(args,false); + histogram_enabled = value; + for (size_t i = 0; i < procs.size(); i++) { + procs[i]->set_histogram(histogram_enabled); + } } -void sim_t::interactive_run(const std::vector& args, bool noisy) +void sim_t::set_procs_debug(bool value) { - if(args.size()) - step_all(atoi(args[0].c_str()),1,noisy); - else - while(1) step_all(1,1,noisy); + for (size_t i=0; i< procs.size(); i++) + procs[i]->set_debug(value); } -void sim_t::interactive_run_proc_noisy(const std::vector& args) +bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes) { - interactive_run_proc(args,true); + if (addr + len < addr) + return false; + return bus.load(addr, len, bytes); } -void sim_t::interactive_run_proc_silent(const std::vector& args) +bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) { - interactive_run_proc(args,false); + if (addr + len < addr) + return false; + return bus.store(addr, len, bytes); } -void sim_t::interactive_run_proc(const std::vector& a, bool noisy) +static std::string dts_compile(const std::string& dts) { - if(a.size() == 0) - return; + // Convert the DTS to DTB + int dts_pipe[2]; + pid_t dts_pid; - int p = atoi(a[0].c_str()); - if(p >= (int)procs.size()) - return; - - if(a.size() == 2) - procs[p].step(atoi(a[1].c_str()),noisy); - else - while(1) procs[p].step(1,noisy); -} + if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) { + std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl; + exit(1); + } -void sim_t::interactive_quit(const std::vector& args) -{ - exit(0); -} + // Child process to output dts + if (dts_pid == 0) { + close(dts_pipe[0]); + int step, len = dts.length(); + const char *buf = dts.c_str(); + for (int done = 0; done < len; done += step) { + step = write(dts_pipe[1], buf+done, len-done); + if (step == -1) { + std::cerr << "Failed to write dts: " << strerror(errno) << std::endl; + exit(1); + } + } + close(dts_pipe[1]); + exit(0); + } -reg_t sim_t::get_pc(const std::vector& args) -{ - if(args.size() != 1) - throw trap_illegal_instruction; + pid_t dtb_pid; + int dtb_pipe[2]; + if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) { + std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl; + exit(1); + } - int p = atoi(args[0].c_str()); - if(p >= (int)procs.size()) - throw trap_illegal_instruction; + // Child process to output dtb + if (dtb_pid == 0) { + dup2(dts_pipe[0], 0); + dup2(dtb_pipe[1], 1); + close(dts_pipe[0]); + close(dts_pipe[1]); + close(dtb_pipe[0]); + close(dtb_pipe[1]); + execl(DTC, DTC, "-O", "dtb", 0); + std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl; + exit(1); + } - return procs[p].pc; -} + close(dts_pipe[1]); + close(dts_pipe[0]); + close(dtb_pipe[1]); -reg_t sim_t::get_reg(const std::vector& args) -{ - if(args.size() != 2) - throw trap_illegal_instruction; + // Read-out dtb + std::stringstream dtb; - int p = atoi(args[0].c_str()); - int r = atoi(args[1].c_str()); - if(p >= (int)procs.size() || r >= NGPR) - throw trap_illegal_instruction; + int got; + char buf[4096]; + while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) { + dtb.write(buf, got); + } + if (got == -1) { + std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl; + exit(1); + } + close(dtb_pipe[0]); + + // Reap children + int status; + waitpid(dts_pid, &status, 0); + if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { + std::cerr << "Child dts process failed" << std::endl; + exit(1); + } + waitpid(dtb_pid, &status, 0); + if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { + std::cerr << "Child dtb process failed" << std::endl; + exit(1); + } - return procs[p].R[r]; + return dtb.str(); } -void sim_t::interactive_reg(const std::vector& args) +void sim_t::make_dtb() { - printf("0x%016llx\n",(unsigned long long)get_reg(args)); + reg_t rtc_addr = EXT_IO_BASE; + bus.add_device(rtc_addr, rtc.get()); + + const int align = 0x1000; + reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align; + reg_t cpu_size = align; + + uint32_t reset_vec[] = { + 0x297 + DRAM_BASE - DEFAULT_RSTVEC, // auipc t0, DRAM_BASE + 0x597, // auipc a1, 0 + 0x58593, // addi a1, a1, 0 + 0xf1402573, // csrr a0,mhartid + 0x00028067 // jalr zero, t0, 0 (jump straight to DRAM_BASE) + }; + reset_vec[2] += (sizeof(reset_vec) - 4) << 20; // addi a1, a1, sizeof(reset_vec) - 4 = DTB start + + std::vector rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec)); + + std::stringstream s; + s << std::dec << + "/dts-v1/;\n" + "\n" + "/ {\n" + " #address-cells = <2>;\n" + " #size-cells = <2>;\n" + " compatible = \"ucbbar,spike-bare-dev\";\n" + " model = \"ucbbar,spike-bare\";\n" + " cpus {\n" + " #address-cells = <1>;\n" + " #size-cells = <0>;\n" + " timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n"; + for (size_t i = 0; i < procs.size(); i++) { + s << " CPU" << i << ": cpu@" << i << " {\n" + " device_type = \"cpu\";\n" + " reg = <" << i << ">;\n" + " status = \"okay\";\n" + " compatible = \"riscv\";\n" + " riscv,isa = \"" << procs[i]->isa_string << "\";\n" + " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n" + " clock-frequency = <" << CPU_HZ << ">;\n" + " interrupt-controller;\n" + " #interrupt-cells = <1>;\n" + " };\n"; + } + reg_t membs = DRAM_BASE; + s << std::hex << + " };\n" + " memory@" << DRAM_BASE << " {\n" + " device_type = \"memory\";\n" + " reg = <0x" << (membs >> 32) << " 0x" << (membs & (uint32_t)-1) << + " 0x" << (memsz >> 32) << " 0x" << (memsz & (uint32_t)-1) << ">;\n" + " };\n" + " soc {\n" + " #address-cells = <2>;\n" + " #size-cells = <2>;\n" + " compatible = \"ucbbar,spike-bare-soc\";\n" + " ranges;\n" + " clint@" << rtc_addr << " {\n" + " compatible = \"riscv,clint0\";\n" + " interrupts-extended = <" << std::dec; + for (size_t i = 0; i < procs.size(); i++) + s << "&CPU" << i << " 3 &CPU" << i << " 7 "; + s << std::hex << ">;\n" + " reg = <0x" << (rtc_addr >> 32) << " 0x" << (rtc_addr & (uint32_t)-1) << + " 0x0 0x10000>;\n" + " };\n" + " };\n" + "};\n"; + + dts = s.str(); + std::string dtb = dts_compile(dts); + + rom.insert(rom.end(), dtb.begin(), dtb.end()); + rom.resize((rom.size() / align + 1) * align); + + boot_rom.reset(new rom_device_t(rom)); + bus.add_device(DEFAULT_RSTVEC, boot_rom.get()); } -reg_t sim_t::get_mem(const std::vector& args) -{ - if(args.size() != 1) - throw trap_illegal_instruction; +// htif - reg_t addr = strtol(args[0].c_str(),NULL,16), val; - mmu_t mmu(mem,memsz); - switch(addr % 8) - { - case 0: - val = mmu.load_uint64(addr); - break; - case 4: - val = mmu.load_uint32(addr); - break; - case 2: - case 6: - val = mmu.load_uint16(addr); - break; - default: - val = mmu.load_uint8(addr); - break; - } - return val; +void sim_t::idle() +{ + target.switch_to(); } -void sim_t::interactive_mem(const std::vector& args) +void sim_t::read_chunk(addr_t taddr, size_t len, void* dst) { - printf("0x%016llx\n",(unsigned long long)get_mem(args)); + assert(len == 8); + auto data = debug_mmu->load_uint64(taddr); + memcpy(dst, &data, sizeof data); } -void sim_t::interactive_until(const std::vector& args) +void sim_t::write_chunk(addr_t taddr, size_t len, const void* src) { - if(args.size() < 3) - return; - - std::string cmd = args[0]; - reg_t val = strtol(args[args.size()-1].c_str(),NULL,16); - - std::vector args2; - args2 = std::vector(args.begin()+1,args.end()-1); - - while(1) - { - reg_t current; - if(args[0] == "reg") - current = get_reg(args2); - else if(args[0] == "pc") - current = get_pc(args2); - else if(args[0] == "mem") - current = get_mem(args2); - else - return; - - if(current == val) - break; - - step_all(1,1,false); - } + assert(len == 8); + uint64_t data; + memcpy(&data, src, sizeof data); + debug_mmu->store_uint64(taddr, data); }