X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fsimif.h;fp=riscv%2Fsimif.h;h=1d982b3396c3edb1f0404138eaff0c03febb8e19;hb=d6fcfdebf6a893bf37670fd67203d18653df4a0e;hp=0000000000000000000000000000000000000000;hpb=19efe7d1121ab0e1a3014a1554e7340fa958c13f;p=riscv-isa-sim.git

diff --git a/riscv/simif.h b/riscv/simif.h
new file mode 100644
index 0000000..1d982b3
--- /dev/null
+++ b/riscv/simif.h
@@ -0,0 +1,21 @@
+// See LICENSE for license details.
+
+#ifndef _RISCV_SIMIF_H
+#define _RISCV_SIMIF_H
+
+#include "decode.h"
+
+// this is the interface to the simulator used by the processors and memory
+class simif_t
+{
+public:
+  // should return NULL for MMIO addresses
+  virtual char* addr_to_mem(reg_t addr) = 0;
+  // used for MMIO addresses
+  virtual bool mmio_load(reg_t addr, size_t len, uint8_t* bytes) = 0;
+  virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0;
+  // Callback for processors to let the simulation know they were reset.
+  virtual void proc_reset(unsigned id) = 0;
+};
+
+#endif