X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Ftrap.h;fp=riscv%2Ftrap.h;h=9a1a2f91e9e9afd5b27aa9c61cb23e839bbf5158;hb=0f140bcde46a940f76d3e06857d3f572ab6966c4;hp=a7a823bcd3fc6479bfd9023dfb3ec99befaf56d0;hpb=289e2118cb35c023c04085e731952edb70fc18a9;p=riscv-isa-sim.git

diff --git a/riscv/trap.h b/riscv/trap.h
index a7a823b..9a1a2f9 100644
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -25,6 +25,7 @@ class mem_trap_t : public trap_t
   mem_trap_t(reg_t which, reg_t badvaddr)
     : trap_t(which), badvaddr(badvaddr) {}
   void side_effects(state_t* state);
+  reg_t get_badvaddr() { return badvaddr; }
  private:
   reg_t badvaddr;
 };
@@ -53,8 +54,5 @@ DECLARE_MEM_TRAP(8, load_address_misaligned)
 DECLARE_MEM_TRAP(9, store_address_misaligned)
 DECLARE_MEM_TRAP(10, load_access_fault)
 DECLARE_MEM_TRAP(11, store_access_fault)
-DECLARE_TRAP(12, vector_disabled)
-DECLARE_TRAP(13, vector_bank)
-DECLARE_TRAP(14, vector_illegal_instruction)
 
 #endif