X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=setup.py;h=1e3eca4413035ac709590839a4b24b20b713e03b;hb=6fcbf10eb9b0be18d5bd08bdad1d55c3ccc9a3f8;hp=0b5d70f70df96dab819376dafb6da2b013dcdd89;hpb=8935ca2c9fd08e5456871b34d2733c92195254cc;p=litex.git

diff --git a/setup.py b/setup.py
index 0b5d70f7..1e3eca44 100755
--- a/setup.py
+++ b/setup.py
@@ -5,22 +5,20 @@ from setuptools import setup
 from setuptools import find_packages
 
 
-required_version = (3, 3)
-if sys.version_info < required_version:
-    raise SystemExit("Migen requires python {0} or greater".format(
-        ".".join(map(str, required_version))))
+if sys.version_info[:3] < (3, 5):
+    raise SystemExit("You need Python 3.5+")
+
 
 setup(
-    name="migen",
-    version="1.0",
-    description="Python toolbox for building complex digital hardware",
-    long_description=open("README.rst").read(),
-    author="Sebastien Bourdeauducq",
-    author_email="sb@m-labs.hk",
-    url="http://m-labs.hk",
-    download_url="https://github.com/m-labs/migen",
-    packages=find_packages(),
-    test_suite="migen.test",
+    name="litex",
+    version="0.2.dev",
+    description="Python tools to design FPGA cores and SoCs",
+    long_description=open("README").read(),
+    author="Florent Kermarrec",
+    author_email="florent@enjoy-digital.fr",
+    url="http://enjoy-digital.fr",
+    download_url="https://github.com/enjoy-digital/litex",
+    test_suite="test",
     license="BSD",
     platforms=["Any"],
     keywords="HDL ASIC FPGA hardware design",
@@ -33,4 +31,21 @@ setup(
         "Operating System :: OS Independent",
         "Programming Language :: Python",
     ],
+    packages=find_packages(exclude=("test*", "sim*", "doc*")),
+    install_requires=["pyserial"],
+    include_package_data=True,
+    entry_points={
+        "console_scripts": [
+            # full names
+            "litex_term=litex.tools.litex_term:main",
+            "litex_server=litex.tools.litex_server:main",
+            "litex_sim=litex.tools.litex_sim:main",
+            "litex_read_verilog=litex.tools.litex_read_verilog:main",
+            "litex_simple=litex.boards.targets.simple:main",
+            # short names
+            "lxterm=litex.tools.litex_term:main",
+            "lxserver=litex.tools.litex_server:main",
+            "lxsim=litex.tools.litex_sim:main",
+        ],
+    },
 )