X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=setup.py;h=59d07529373a517ea6a6123312fec9865cbc299f;hb=3e1b17d459c1966dd561ad5262a7cb9299575191;hp=d248834b6d13697c331a5dfac4a8da7a1cfb1463;hpb=69764f2e22b22fff3ca96b978d492ed70df3b1ab;p=litex.git diff --git a/setup.py b/setup.py index d248834b..59d07529 100755 --- a/setup.py +++ b/setup.py @@ -1,30 +1,27 @@ #!/usr/bin/env python3 -import sys -import os from setuptools import setup from setuptools import find_packages -here = os.path.abspath(os.path.dirname(__file__)) -README = open(os.path.join(here, "README.md")).read() - -required_version = (3, 3) -if sys.version_info < required_version: - raise SystemExit("Migen requires python {0} or greater".format( - ".".join(map(str, required_version)))) setup( - name="migen", - version="unknown", - description="Python toolbox for building complex digital hardware", - long_description=README, - author="Sebastien Bourdeauducq", - author_email="sb@m-labs.hk", - url="http://m-labs.hk", - download_url="https://github.com/m-labs/migen", - packages=find_packages(here), - test_suite="migen.test", + name="litex", + description="Python SoC/Core builder for building FPGA based systems.", + author="Florent Kermarrec", + author_email="florent@enjoy-digital.fr", + url="http://enjoy-digital.fr", + download_url="https://github.com/enjoy-digital/litex", + test_suite="test", license="BSD", + python_requires="~=3.6", + install_requires=[ + "migen", + "pyserial", + "requests", + "pythondata-software-compiler_rt", + ], + packages=find_packages(exclude=("test*", "sim*", "doc*")), + include_package_data=True, platforms=["Any"], keywords="HDL ASIC FPGA hardware design", classifiers=[ @@ -36,4 +33,20 @@ setup( "Operating System :: OS Independent", "Programming Language :: Python", ], + entry_points={ + "console_scripts": [ + # full names + "litex_term=litex.tools.litex_term:main", + "litex_server=litex.tools.litex_server:main", + "litex_jtag_uart=litex.tools.litex_jtag_uart:main", + "litex_crossover_uart=litex.tools.litex_crossover_uart:main", + "litex_sim=litex.tools.litex_sim:main", + "litex_read_verilog=litex.tools.litex_read_verilog:main", + "litex_simple=litex.boards.targets.simple:main", + # short names + "lxterm=litex.tools.litex_term:main", + "lxserver=litex.tools.litex_server:main", + "lxsim=litex.tools.litex_sim:main", + ], + }, )