X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=shakti%2Fm_class%2FDDR.mdwn;h=d1d21080626f22bfde469387461be8a9eed9075b;hb=c4fc037dc1d51ae0858d732b57b292d9ff25d065;hp=8bae234cc3bff39075673eb10ca6cdbbb57074e6;hpb=ff3053614b027c7160e9ec66c93c7668d2632f04;p=libreriscv.git

diff --git a/shakti/m_class/DDR.mdwn b/shakti/m_class/DDR.mdwn
index 8bae234cc..d1d210806 100644
--- a/shakti/m_class/DDR.mdwn
+++ b/shakti/m_class/DDR.mdwn
@@ -1,3 +1,9 @@
 # DDR (DRAM) Controller and PHY
 
 * <https://github.com/enjoy-digital/litedram> - controller inc. DDR3 / LPDDR3
+* <https://www.ohwr.org/projects/ddr3-sp6-core/wiki/wiki> - CERN DDR3 ctrl
+* <https://www.linkedin.com/in/michael-taylor-32212816/> working on DDR3 IO Cells
+* <https://github.com/waviousllc/wav-lpddr-hw>
+* <https://github.com/ZiyangYE/General-Slow-DDR3-Interface>
+* <https://github.com/ultraembedded/core_ddr3_controller>
+