X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=shakti%2Fm_class.mdwn;h=3fd955b622eb15954d262161eadfbc74672be8e5;hb=ee952ab4310451ada3fdb590864abf39b23e16f0;hp=ef21a51c00ba1fe4786148900061c9cb5e6c295b;hpb=170469fd4d1ace1f16ad782ab79cb310f6d42230;p=libreriscv.git

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index ef21a51c0..3fd955b62 100644
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -14,8 +14,8 @@ yields.
 
 ## Rough specification.
 
-Quad-core 28nm RISC-V 64-bit (RISCV64GC core with Vector SIMD Media / 3D
-extensions), 300-pin 15x15mm BGA 0.8mm pitch, 32-bit DDR3/DDR3L/LPDDR3
+Quad-core 28nm OpenPOWER 64-bit (OpenPOWER v3.0B core with Simple-V Vector Media / 3D
+extensions), 300-pin 15x15mm BGA 0.8mm pitch, 32-bit DDR3-4/LPDDR3/4
 memory interface and libre / open interfaces and accelerated hardware
 functions suitable for the higher-end, low-power, embedded, industrial
 and mobile space.
@@ -40,7 +40,7 @@ The only barrier to being able to replicate the masks from scratch
 is the proprietary cells (e.g. memory cells) designed by the Foundries:
 there is a potential long-term strategy in place to deal with that issue.
 
-The only proprietary interface utilised in the entire SoC is the DDR3
+The only proprietary interface utilised in the entire SoC is the DDR3/4
 PHY plus Controller, which will be replaced in a future revision, making
 the entire SoC exclusively designed and made from fully libre-licensed
 BSD and LGPL openly and freely accessible VLSI and VHDL source.
@@ -48,7 +48,7 @@ BSD and LGPL openly and freely accessible VLSI and VHDL source.
 In addition, no proprietary firmware whatsoever will be required to
 operate or boot the device right from the bedrock: the entire software
 stack will also be libre-licensed (even for programming the initial
-proprietary DDR3 PHY+Controller)
+proprietary DDR3/4 PHY+Controller)
 
 # Inspiration from several sources
 
@@ -99,7 +99,7 @@ firmly a priority focus.
 
 ## Common Peripherals to majority of target markets
 
-* SPI or 8080 or RGB/TTL or LVDS LCD display.  SPI: 320x240.  LVDS: 1440x900.
+* SPI or 8080 or [RGB/TTL](RGBTTL) or LVDS LCD display.  SPI: 320x240.  LVDS: 1440x900.
 * LCD Backlight, requires GPIO power-control plus PWM for brightness control
 * USB-OTG Port (OTG-Host, OTG Client, Charging capability)
 * Baseband Modem (GSM / GPRS / 3G / LTE) requiring USB, UART, and PCM audio
@@ -120,6 +120,7 @@ firmly a priority focus.
 * [[PCIe]] via PXPIPE
 * [[LPC]] from Raptor Engineering
 * [[USB3]]
+* [[RGMII]] Gigabit Ethernet
 
 ## Peripherals unique to laptop market
 
@@ -128,13 +129,13 @@ firmly a priority focus.
 
 ## Peripherals common to laptop and Industrial Market
 
-* Ethernet (RGMII or better 8080-style XT/AT/ATI MCU bus)
+* Ethernet ([[RGMII]] or better 8080-style XT/AT/ATI MCU bus for e.g. DM9000)
 
 ## Augmentation by an embedded MCU
 
 Some functions, particularly analog, are particularly tricky to implement
-in an early SoC.  In addition, CAN is still patented.  For unusual, patented
-or analog functionality such as CAN, RTC, ADC, DAC, SPDIF, One-wire Bus
+in an early SoC.  In addition, CAN is still patented (not any more).  For unusual, patented
+or analog functionality such as RTC, ADC, DAC, SPDIF, One-wire Bus
 and so on it is easier and simpler to deploy an ultra-low-cost low-speed
 companion Micro-Controller such as the crystal-less STMS8003 ($0.24) or
 the crystal-less STM32F072 or other suitable MCU, depending on requirements.
@@ -177,11 +178,13 @@ image acceleration, scalable fonts, and Z-buffering and much more.
 
 <https://opencores.org/project,orsoc_graphics_accelerator>
 
+<https://github.com/m-labs/milkymist/tree/master/cores/tmu2>
+
 ### 3D acceleration
 
 * MIAOW: ATI-compatible shader engine <http://miaowgpu.org/>
 * ORSOC GPU contains some primitives that can be used
-* SIMD RISC-V extensions can obviate the need for a "full" separate GPU
+* Simple-V Vector extensions can obviate the need for a "full" separate GPU
 * Nyuzi (OpenMP, based on Intel Larabee Compute Engine)
 * Rasteriser <https://github.com/jbush001/ChiselGPU/tree/master/hardware>
 * OpenShader <https://git.code.sf.net/p/openshader/code>
@@ -220,7 +223,7 @@ TBD
 * 3x [[PWM]]-capable GPIO
 * 32x [[EINT]]-cable GPIO with full edge-triggered and low/high IRQ capability
 * 1x [[I2S]] audio with 4-wire output and 1-wire input.
-* 3x USB2 (ULPI for reduced pincount) each capable of USB-OTG support
+* 3x [[USB2]] ([[ULPI]] for reduced pincount) each capable of USB-OTG support
 * [[DDR]] DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
 * [[JTAG]] for debugging