X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=shakti%2Fm_class.mdwn;h=9f96863e49c9a176feb060186fd45884a4ff8dee;hb=accf72ba93cb78b88c4f0f0e4463d96ab7fadddf;hp=fb02568d5f91fe968448000cb01222f7b19ddf60;hpb=9c07b7a83de069c387d4c3d37ddd806d87173556;p=libreriscv.git

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index fb02568d5..9f96863e4 100644
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -217,7 +217,7 @@ TBD
 * 32x [[EINT]]-cable GPIO with full edge-triggered and low/high IRQ capability
 * 1x [[I2S]] audio with 4-wire output and 1-wire input.
 * 3x USB2 (ULPI for reduced pincount) each capable of USB-OTG support
-* DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
+* [[DDR]] DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
 * [[JTAG]] for debugging
 
 Some interfaces at:
@@ -234,6 +234,8 @@ Some interfaces at:
 
 List of Interfaces:
 
+* [[CSI]]
+* [[DDR]]
 * [[JTAG]]
 * [[I2C]]
 * [[I2S]]
@@ -351,5 +353,13 @@ many more.
 * <https://level42.ca/projects/ultra64/Documentation/man/pro-man/pro25/index25.1.html>
 * <http://n64devkit.square7.ch/qa/graphics/ucode.htm>
 * <https://dac.com/media-center/exhibitor-news/synopsys%E2%80%99-designware-universal-ddr-memory-controller-delivers-30-percent> 110nm DDR3 PHY
+* <https://bitbucket.org/cfelton/minnesota> myhdl HDL cores
+* B Extension proposal <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/zi_7B15kj6s>
+* Bit-extracts <https://github.com/cliffordwolf/bextdep>
+* Bit-reverse <http://programming.sirrida.de/bit_perm.html#general_reverse_bits>
+* Bit-permutations <http://programming.sirrida.de/bit_perm.html#c_e>
+* Commentary on Micro-controller <https://github.com/emb-riscv/specs-markdown/blob/develop/improvements-upon-privileged.md>
+* P-SIMD <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/vYVi95gF2Mo>
+
+>
 [[!tag cpus]]
-