X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=shakti%2Fm_class.mdwn;h=a624b3eb4c96b472199b79a085e80fd498362a61;hb=d92382167b931f0dd6f72bc88eef6321eaf1d17f;hp=71c65469a971ec55d3ff4eb2ec41bf45a717b6c5;hpb=06998eacf23b38961e5d1408aa036891993feb6e;p=libreriscv.git

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index 71c65469a..a624b3eb4 100644
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -10,6 +10,7 @@ yields.
 * See [[pinouts]] for auto-generated table of pinouts (including mux)
 * See [[peripheralschematics]] for example Reference Layouts
 * See [[ramanalysis]] for a comprehensive analysis of why DDR3 is to be used.
+* See [[todo]] for a rough list of tasks (and link to bugtracker)
 
 ## Rough specification.
 
@@ -24,6 +25,15 @@ to be used (8-10mil) and 4-5mil tracks with 4mil clearance.  For
 details see
 <http://processors.wiki.ti.com/index.php/General_hardware_design/BGA_PCB_design>
 
+[[shakti_libre_riscv.jpg]]
+
+## Die area estimates
+
+* <http://hwacha.org/papers/riscv-esscirc2014-talk.pdf>
+* 40nm 64-bit rocket single-core single-issue in-order: 0.14mm^2
+* 40nm 16-16k L1 caches, 0.25mm^2
+* <http://people.csail.mit.edu/beckmann/publications/tech.../grain_size_tr_feb_2010.pdf>
+
 ## Targetting full Libre Licensing to the bedrock.
 
 The only barrier to being able to replicate the masks from scratch
@@ -98,7 +108,7 @@ firmly a priority focus.
 * SD/MMC for external MicroSD
 * SD/MMC for on-PCB eMMC (care needed on power/boot sequence)
 * NAND Flash (not recommended), requires 8080/ATI-style Bus with dedicated CS#
-* Optional 4-wire SPI NAND/NOR for boot (XIP - Execute In-place - recommended).
+* Optional 4-wire [[QSPI]] NAND/NOR for boot (XIP - Execute In-place - recommended).
 * Audio over [[I2S]] (5-pin: 4 for output, 1 for input), fall-back to USB Audio
 * Audio also over [[AC97]]
 * Some additional SPI peripherals, e.g. connection to low-power MCU.
@@ -107,6 +117,8 @@ firmly a priority focus.
 * I2C sensors: accelerometer, compass, etc.  Each requires EINT and RST GPIO.
 * Capacitive Touchpanel (I2C and also requiring EINT and RST GPIO)
 * Real-time Clock (usually an I2C device but may be on-board a support MCU)
+* [[PCIe]] via PXPIPE
+* [[LPC]] from Raptor Engineering
 
 ## Peripherals unique to laptop market
 
@@ -169,6 +181,10 @@ image acceleration, scalable fonts, and Z-buffering and much more.
 * MIAOW: ATI-compatible shader engine <http://miaowgpu.org/>
 * ORSOC GPU contains some primitives that can be used
 * SIMD RISC-V extensions can obviate the need for a "full" separate GPU
+* Nyuzi (OpenMP, based on Intel Larabee Compute Engine)
+* Rasteriser <https://github.com/jbush001/ChiselGPU/tree/master/hardware>
+* OpenShader <https://git.code.sf.net/p/openshader/code>
+* GPLGPU <https://github.com/asicguy/gplgpu>
 
 ### Video encode / decode
 
@@ -190,19 +206,21 @@ TBD
 
 # Proposed Interfaces
 
+* Plain [[GPIO]] multiplexed with a [[pinmux]] onto (nearly) all other pins
 * RGB/TTL up to 1440x900 @ 60fps, 24-bit colour
-* 2x 1-lane SPI
-* 1x 4-lane (quad) SPI
+* 2x 1-lane [[SPI]]
+* 1x 4-lane (quad) [[QSPI]]
 * 4x SD/MMC (1x 1/2/4/8-bit, 3x 1/2/4-bit)
-* 2x full UART incl. CTS/RTS
-* 3x UART (TX/RX only)
+* 2x full [[UART]] incl. CTS/RTS
+* 3x [[UART]] (TX/RX only)
 * 3x [[I2C]] (in case of address clashes between peripherals)
 * 8080-style AT/XT/ATI MCU Bus Interface, with multiple (8x CS#) lines
 * 3x [[PWM]]-capable GPIO
 * 32x [[EINT]]-cable GPIO with full edge-triggered and low/high IRQ capability
 * 1x [[I2S]] audio with 4-wire output and 1-wire input.
 * 3x USB2 (ULPI for reduced pincount) each capable of USB-OTG support
-* DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
+* [[DDR]] DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
+* [[JTAG]] for debugging
 
 Some interfaces at:
 
@@ -212,9 +230,15 @@ Some interfaces at:
   is a Watchdog Timer and others.
 * <https://github.com/sifive/freedom/blob/master/src/main/scala/everywhere/e300artydevkit/Platform.scala>
   Pinmux ("IOF") for multiplexing several I/O functions onto a single pin
+* <https://bitbucket.org/casl/c-class/src/0e77398a030bfd705930d0f1b8b9b5050d76e265/src/peripherals/?at=master>
+  including AXI, DMA, GPIO, I2C, JTAG, PLIC, QSPI, SDRAM, UART (and TCM?).
+  FlexBus, HyperBus and xSPI to be added.
 
 List of Interfaces:
 
+* [[CSI]]
+* [[DDR]]
+* [[JTAG]]
 * [[I2C]]
 * [[I2S]]
 * [[PWM]]
@@ -222,9 +246,11 @@ List of Interfaces:
 * [[FlexBus]]
 * LCD / RGB/TTL [[RGBTTL]]
 * [[SPI]]
+* [[QSPI]]
 * SD/MMC and eMMC [[sdmmc]]
 * Pin Multiplexing [[pinmux]]
 * Gigabit Ethernet [[RGMII]]
+* SDRAM [[sdram]]
 
 List of Internal Interfaces:
 
@@ -319,10 +345,24 @@ and accurate PLL clock timing provided, it may become possible to bit-bang
 and software-emulate high-speed interfaces such as SATA, HDMI, PCIe and
 many more.
 
+# Testing
+
+* cocotb 
+* <https://github.com/aoeldemann/cocotb> cocotb AXI4 stream interface
+
 # Research (to investigate)
 
+* LPC Interface <https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga>
 * <https://level42.ca/projects/ultra64/Documentation/man/pro-man/pro25/index25.1.html>
 * <http://n64devkit.square7.ch/qa/graphics/ucode.htm>
 * <https://dac.com/media-center/exhibitor-news/synopsys%E2%80%99-designware-universal-ddr-memory-controller-delivers-30-percent> 110nm DDR3 PHY
+* <https://bitbucket.org/cfelton/minnesota> myhdl HDL cores
+* B Extension proposal <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/zi_7B15kj6s>
+* Bit-extracts <https://github.com/cliffordwolf/bextdep>
+* Bit-reverse <http://programming.sirrida.de/bit_perm.html#general_reverse_bits>
+* Bit-permutations <http://programming.sirrida.de/bit_perm.html#c_e>
+* Commentary on Micro-controller <https://github.com/emb-riscv/specs-markdown/blob/develop/improvements-upon-privileged.md>
+* P-SIMD <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/vYVi95gF2Mo>
+
+>
 [[!tag cpus]]
-