X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=shakti%2Fm_class.mdwn;h=ecad472f1c6632761038a665234175b9afa7da63;hb=b5b2d6d2364d6766e53d07826472751427852e36;hp=4209b49b7b49ecf409580aef043e5ea76382af7a;hpb=c15e96b608c8cd9eeeb4223a09df02419d8e012f;p=libreriscv.git diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn index 4209b49b7..ecad472f1 100644 --- a/shakti/m_class.mdwn +++ b/shakti/m_class.mdwn @@ -10,6 +10,7 @@ yields. * See [[pinouts]] for auto-generated table of pinouts (including mux) * See [[peripheralschematics]] for example Reference Layouts * See [[ramanalysis]] for a comprehensive analysis of why DDR3 is to be used. +* See [[todo]] for a rough list of tasks (and link to bugtracker) ## Rough specification. @@ -24,6 +25,15 @@ to be used (8-10mil) and 4-5mil tracks with 4mil clearance. For details see +[[shakti_libre_riscv.jpg]] + +## Die area estimates + +* +* 40nm 64-bit rocket single-core single-issue in-order: 0.14mm^2 +* 40nm 16-16k L1 caches, 0.25mm^2 +* + ## Targetting full Libre Licensing to the bedrock. The only barrier to being able to replicate the masks from scratch @@ -98,15 +108,17 @@ firmly a priority focus. * SD/MMC for external MicroSD * SD/MMC for on-PCB eMMC (care needed on power/boot sequence) * NAND Flash (not recommended), requires 8080/ATI-style Bus with dedicated CS# -* Optional 4-wire SPI NAND/NOR for boot (XIP - Execute In-place - recommended). +* Optional 4-wire [[QSPI]] NAND/NOR for boot (XIP - Execute In-place - recommended). * Audio over [[I2S]] (5-pin: 4 for output, 1 for input), fall-back to USB Audio -* Audio also over AC97 +* Audio also over [[AC97]] * Some additional SPI peripherals, e.g. connection to low-power MCU. * GPIO (EINT-capable, with wakeup) for buttons, power, volume etc. * Camera(s) either by CSI-1 (parallel CSI) or better by USB * I2C sensors: accelerometer, compass, etc. Each requires EINT and RST GPIO. * Capacitive Touchpanel (I2C and also requiring EINT and RST GPIO) * Real-time Clock (usually an I2C device but may be on-board a support MCU) +* [[PCIe]] via PXPIPE +* [[LPC]] from Raptor Engineering ## Peripherals unique to laptop market @@ -169,6 +181,11 @@ image acceleration, scalable fonts, and Z-buffering and much more. * MIAOW: ATI-compatible shader engine * ORSOC GPU contains some primitives that can be used * SIMD RISC-V extensions can obviate the need for a "full" separate GPU +* Nyuzi (OpenMP, based on Intel Larabee Compute Engine) +* Rasteriser +* OpenShader +* GPLGPU +* FlexGripPlus ### Video encode / decode @@ -190,38 +207,51 @@ TBD # Proposed Interfaces +* Plain [[GPIO]] multiplexed with a [[pinmux]] onto (nearly) all other pins * RGB/TTL up to 1440x900 @ 60fps, 24-bit colour -* 2x 1-lane SPI -* 1x 4-lane (quad) SPI +* 2x 1-lane [[SPI]] +* 1x 4-lane (quad) [[QSPI]] * 4x SD/MMC (1x 1/2/4/8-bit, 3x 1/2/4-bit) -* 2x full UART incl. CTS/RTS -* 3x UART (TX/RX only) +* 2x full [[UART]] incl. CTS/RTS +* 3x [[UART]] (TX/RX only) * 3x [[I2C]] (in case of address clashes between peripherals) * 8080-style AT/XT/ATI MCU Bus Interface, with multiple (8x CS#) lines -* 3x PWM-capable GPIO -* 32x EINT-cable GPIO with full edge-triggered and low/high IRQ capability +* 3x [[PWM]]-capable GPIO +* 32x [[EINT]]-cable GPIO with full edge-triggered and low/high IRQ capability * 1x [[I2S]] audio with 4-wire output and 1-wire input. * 3x USB2 (ULPI for reduced pincount) each capable of USB-OTG support -* DDR3/DDR3L/LPDDR3 32-bit-wide memory controller +* [[DDR]] DDR3/DDR3L/LPDDR3 32-bit-wide memory controller +* [[JTAG]] for debugging Some interfaces at: +* * includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM. Also included is a Watchdog Timer and others. * Pinmux ("IOF") for multiplexing several I/O functions onto a single pin +* + including AXI, DMA, GPIO, I2C, JTAG, PLIC, QSPI, SDRAM, UART (and TCM?). + FlexBus, HyperBus and xSPI to be added. List of Interfaces: +* [[CSI]] +* [[DDR]] +* [[JTAG]] * [[I2C]] * [[I2S]] +* [[PWM]] +* [[EINT]] * [[FlexBus]] * LCD / RGB/TTL [[RGBTTL]] * [[SPI]] +* [[QSPI]] * SD/MMC and eMMC [[sdmmc]] * Pin Multiplexing [[pinmux]] * Gigabit Ethernet [[RGMII]] +* SDRAM [[sdram]] List of Internal Interfaces: @@ -316,10 +346,24 @@ and accurate PLL clock timing provided, it may become possible to bit-bang and software-emulate high-speed interfaces such as SATA, HDMI, PCIe and many more. +# Testing + +* cocotb +* cocotb AXI4 stream interface + # Research (to investigate) +* LPC Interface * * * 110nm DDR3 PHY +* myhdl HDL cores +* B Extension proposal +* Bit-extracts +* Bit-reverse +* Bit-permutations +* Commentary on Micro-controller +* P-SIMD + +> [[!tag cpus]] -