X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=sim%2Fcommon%2Fsim-core.h;h=14725fb0ab980a7113993acbb1ec16a980260bb6;hb=fc0a224429224e8ce0c1adb631e10124a597cc6d;hp=ef6b3f18187cceb96ba4dff7369aeb7651fdb9f6;hpb=fcc86d82f7864c9609d2a02acb1a25074e9902ed;p=binutils-gdb.git diff --git a/sim/common/sim-core.h b/sim/common/sim-core.h index ef6b3f18187..14725fb0ab9 100644 --- a/sim/common/sim-core.h +++ b/sim/common/sim-core.h @@ -1,29 +1,34 @@ -/* This file is part of the program psim. +/* The common simulator framework for GDB, the GNU Debugger. - Copyright (C) 1994-1997, Andrew Cagney + Copyright 2002 Free Software Foundation, Inc. - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. + Contributed by Andrew Cagney and Red Hat. - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - - */ + This file is part of GDB. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. -#ifndef _SIM_CORE_H_ -#define _SIM_CORE_H_ + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ -/* core signals (error conditions) */ + +#ifndef SIM_CORE_H +#define SIM_CORE_H + + +/* core signals (error conditions) + Define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for + details. */ typedef enum { sim_core_unmapped_signal, @@ -31,9 +36,12 @@ typedef enum { nr_sim_core_signals, } sim_core_signals; -/* define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for - details */ +/* Type of SIM_CORE_SIGNAL handler. */ +typedef void (SIM_CORE_SIGNAL_FN) + (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, unsigned map, int nr_bytes, + address_word addr, transfer_type transfer, sim_core_signals sig); +extern SIM_CORE_SIGNAL_FN sim_core_signal; /* basic types */ @@ -51,7 +59,11 @@ struct _sim_core_mapping { void *free_buffer; void *buffer; /* callback map */ +#if (WITH_HW) + struct hw *device; +#else device *device; +#endif /* tracing */ int trace; /* growth */ @@ -63,16 +75,9 @@ struct _sim_core_map { sim_core_mapping *first; }; -typedef enum { - sim_core_read_map, - sim_core_write_map, - sim_core_execute_map, - nr_sim_core_maps, -} sim_core_maps; - typedef struct _sim_core_common { - sim_core_map map[nr_sim_core_maps]; + sim_core_map map[nr_maps]; } sim_core_common; @@ -96,54 +101,65 @@ typedef struct _sim_cpu_core { /* Install the "core" module. */ -EXTERN_SIM_CORE\ -(SIM_RC) sim_core_install (SIM_DESC sd); +extern SIM_RC sim_core_install (SIM_DESC sd); -/* Create a memory space within the core. +/* Create a memory region within the core. - CPU, when non NULL, specifes the single processor that the memory - space is to be attached to. (UNIMPLEMENTED). + CPU - when non NULL, specifes the single processor that the memory + space is to be attached to. (INIMPLEMENTED). - LEVEL specifies the ordering of the memory region. Lower regions + LEVEL - specifies the ordering of the memory region. Lower regions are searched first. Within a level, memory regions can not overlap. - DEVICE, when non NULL, specifies a callback memory space. - (UNIMPLEMENTED, see the ppc simulator for an example). + MAPMASK - Bitmask specifying the memory maps that the region is to + be attached to. Typically the enums sim-basics.h:access_* are used. - MODULO, when the simulator has been configured WITH_MODULO support + ADDRESS_SPACE - For device regions, a MAP:ADDRESS pair is + translated into ADDRESS_SPACE:OFFSET before being passed to the + client device. + + MODULO - when the simulator has been configured WITH_MODULO support and is greater than zero, specifies that accesses to the region [ADDR .. ADDR+NR_BYTES) should be mapped onto the sub region [ADDR .. ADDR+MODULO). The modulo value must be a power of two. - OPTIONAL_BUFFER, when non NULL, specifies the buffer to use for + DEVICE - When non NULL, indicates that this is a callback memory + space and specified device's memory callback handler should be + called. + + OPTIONAL_BUFFER - when non NULL, specifies the buffer to use for data read & written to the region. Normally a more efficient internal structure is used. It is assumed that buffer is allocated such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis - (OPTIONAL_BUFFER % 8) == (ADDR % 8)) */ + (OPTIONAL_BUFFER % 8) == (ADDR % 8)). It is defined to be a sub-optimal + hook that allows clients to do nasty things that the interface doesn't + accomodate. */ -EXTERN_SIM_CORE\ -(void) sim_core_attach +extern void sim_core_attach (SIM_DESC sd, sim_cpu *cpu, int level, - access_type access, + unsigned mapmask, int address_space, address_word addr, address_word nr_bytes, unsigned modulo, +#if (WITH_HW) + struct hw *client, +#else device *client, +#endif void *optional_buffer); -/* Delete a memory space within the core. +/* Delete a memory section within the core. */ -EXTERN_SIM_CORE\ -(void) sim_core_detach +extern void sim_core_detach (SIM_DESC sd, sim_cpu *cpu, int level, @@ -154,7 +170,7 @@ EXTERN_SIM_CORE\ /* Variable sized read/write Transfer a variable sized block of raw data between the host and - target. Should any problems occure, the number of bytes + target. Should any problems occur, the number of bytes successfully transfered is returned. No host/target byte endian conversion is performed. No xor-endian @@ -164,20 +180,18 @@ EXTERN_SIM_CORE\ address map that is to be used in the transfer. */ -EXTERN_SIM_CORE\ -(unsigned) sim_core_read_buffer +extern unsigned sim_core_read_buffer (SIM_DESC sd, sim_cpu *cpu, - sim_core_maps map, + unsigned map, void *buffer, address_word addr, unsigned nr_bytes); -EXTERN_SIM_CORE\ -(unsigned) sim_core_write_buffer +extern unsigned sim_core_write_buffer (SIM_DESC sd, sim_cpu *cpu, - sim_core_maps map, + unsigned map, const void *buffer, address_word addr, unsigned nr_bytes); @@ -193,8 +207,7 @@ EXTERN_SIM_CORE\ The CPU argument, when non NULL, specifes the single processor that the xor-endian configuration is to be applied to. */ -EXTERN_SIM_CORE\ -(void) sim_core_set_xor\ +extern void sim_core_set_xor (SIM_DESC sd, sim_cpu *cpu, int is_xor); @@ -203,7 +216,7 @@ EXTERN_SIM_CORE\ /* XOR version of variable sized read/write. Transfer a variable sized block of raw data between the host and - target. Should any problems occure, the number of bytes + target. Should any problems occur, the number of bytes successfully transfered is returned. No host/target byte endian conversion is performed. If applicable @@ -213,20 +226,18 @@ EXTERN_SIM_CORE\ If CPU argument, when non NULL, specifies the processor specific address map that is to be used in the transfer. */ -EXTERN_SIM_CORE\ -(unsigned) sim_core_xor_read_buffer +extern unsigned sim_core_xor_read_buffer (SIM_DESC sd, sim_cpu *cpu, - sim_core_maps map, + unsigned map, void *buffer, address_word addr, unsigned nr_bytes); -EXTERN_SIM_CORE\ -(unsigned) sim_core_xor_write_buffer +extern unsigned sim_core_xor_write_buffer (SIM_DESC sd, sim_cpu *cpu, - sim_core_maps map, + unsigned map, const void *buffer, address_word addr, unsigned nr_bytes); @@ -240,38 +251,45 @@ EXTERN_SIM_CORE\ order (including xor endian). Should the transfer fail, the operation shall abort (no return). - The aligned alternative makes the assumption that that the address - is N byte aligned (no alignment checks are made). + ALIGNED assumes yhat the specified ADDRESS is correctly alligned + for an N byte transfer (no alignment checks are made). Passing an + incorrectly aligned ADDRESS is erroneous. + + UNALIGNED checks/modifies the ADDRESS according to the requirements + of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being + taken should the check fail. - The unaligned alternative checks the address for correct byte - alignment. Action, as defined by WITH_ALIGNMENT, being taken - should the check fail. + MISSALIGNED transfers the data regardless. Misaligned xor-endian accesses are broken into a sequence of transfers each <= WITH_XOR_ENDIAN bytes */ -#define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N) \ +#define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N,M) \ INLINE_SIM_CORE\ (void) sim_core_write_##ALIGNMENT##_##N \ (sim_cpu *cpu, \ sim_cia cia, \ - sim_core_maps map, \ + unsigned map, \ address_word addr, \ - unsigned_##N val); + unsigned_##M val); -DECLARE_SIM_CORE_WRITE_N(aligned,1) -DECLARE_SIM_CORE_WRITE_N(aligned,2) -DECLARE_SIM_CORE_WRITE_N(aligned,4) -DECLARE_SIM_CORE_WRITE_N(aligned,8) -DECLARE_SIM_CORE_WRITE_N(aligned,16) +DECLARE_SIM_CORE_WRITE_N(aligned,1,1) +DECLARE_SIM_CORE_WRITE_N(aligned,2,2) +DECLARE_SIM_CORE_WRITE_N(aligned,4,4) +DECLARE_SIM_CORE_WRITE_N(aligned,8,8) +DECLARE_SIM_CORE_WRITE_N(aligned,16,16) -DECLARE_SIM_CORE_WRITE_N(unaligned,1) -DECLARE_SIM_CORE_WRITE_N(unaligned,2) -DECLARE_SIM_CORE_WRITE_N(unaligned,4) -DECLARE_SIM_CORE_WRITE_N(unaligned,8) -DECLARE_SIM_CORE_WRITE_N(unaligned,16) +#define sim_core_write_unaligned_1 sim_core_write_aligned_1 +DECLARE_SIM_CORE_WRITE_N(unaligned,2,2) +DECLARE_SIM_CORE_WRITE_N(unaligned,4,4) +DECLARE_SIM_CORE_WRITE_N(unaligned,8,8) +DECLARE_SIM_CORE_WRITE_N(unaligned,16,16) +DECLARE_SIM_CORE_WRITE_N(misaligned,3,4) +DECLARE_SIM_CORE_WRITE_N(misaligned,5,8) +DECLARE_SIM_CORE_WRITE_N(misaligned,6,8) +DECLARE_SIM_CORE_WRITE_N(misaligned,7,8) #define sim_core_write_1 sim_core_write_aligned_1 #define sim_core_write_2 sim_core_write_aligned_2 @@ -286,25 +304,31 @@ DECLARE_SIM_CORE_WRITE_N(unaligned,16) #undef DECLARE_SIM_CORE_WRITE_N -#define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N) \ +#define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N,M) \ INLINE_SIM_CORE\ -(unsigned_##N) sim_core_read_##ALIGNMENT##_##N \ +(unsigned_##M) sim_core_read_##ALIGNMENT##_##N \ (sim_cpu *cpu, \ sim_cia cia, \ - sim_core_maps map, \ + unsigned map, \ address_word addr); -DECLARE_SIM_CORE_READ_N(aligned,1) -DECLARE_SIM_CORE_READ_N(aligned,2) -DECLARE_SIM_CORE_READ_N(aligned,4) -DECLARE_SIM_CORE_READ_N(aligned,8) -DECLARE_SIM_CORE_READ_N(aligned,16) +DECLARE_SIM_CORE_READ_N(aligned,1,1) +DECLARE_SIM_CORE_READ_N(aligned,2,2) +DECLARE_SIM_CORE_READ_N(aligned,4,4) +DECLARE_SIM_CORE_READ_N(aligned,8,8) +DECLARE_SIM_CORE_READ_N(aligned,16,16) + +#define sim_core_read_unaligned_1 sim_core_read_aligned_1 +DECLARE_SIM_CORE_READ_N(unaligned,2,2) +DECLARE_SIM_CORE_READ_N(unaligned,4,4) +DECLARE_SIM_CORE_READ_N(unaligned,8,8) +DECLARE_SIM_CORE_READ_N(unaligned,16,16) + +DECLARE_SIM_CORE_READ_N(misaligned,3,4) +DECLARE_SIM_CORE_READ_N(misaligned,5,8) +DECLARE_SIM_CORE_READ_N(misaligned,6,8) +DECLARE_SIM_CORE_READ_N(misaligned,7,8) -DECLARE_SIM_CORE_READ_N(unaligned,1) -DECLARE_SIM_CORE_READ_N(unaligned,2) -DECLARE_SIM_CORE_READ_N(unaligned,4) -DECLARE_SIM_CORE_READ_N(unaligned,8) -DECLARE_SIM_CORE_READ_N(unaligned,16) #define sim_core_read_1 sim_core_read_aligned_1 #define sim_core_read_2 sim_core_read_aligned_2 @@ -318,4 +342,14 @@ DECLARE_SIM_CORE_READ_N(unaligned,16) #undef DECLARE_SIM_CORE_READ_N + +#if (WITH_DEVICES) +/* TODO: create sim/common/device.h */ +/* These are defined with each particular cpu. */ +void device_error (device *me, char* message, ...); +int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia); +int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia); +#endif + + #endif